Memory: Move all state machine code out to its own always block.
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 `define SWP_READING     2'b01
4 `define SWP_WRITING     2'b10
5
6 `define LSRH_MEMIO      3'b001
7 `define LSRH_BASEWB     3'b010
8 `define LSRH_WBFLUSH    3'b100
9
10 `define LSR_MEMIO       4'b0001
11 `define LSR_STRB_WR     4'b0010
12 `define LSR_BASEWB      4'b0100
13 `define LSR_WBFLUSH     4'b1000
14
15 `define LSM_SETUP       4'b0001
16 `define LSM_MEMIO       4'b0010
17 `define LSM_BASEWB      4'b0100
18 `define LSM_WBFLUSH     4'b1000
19
20
21 module Memory(
22         input clk,
23         input Nrst,
24
25         input flush,
26
27         /* bus interface */
28         output reg [31:0] busaddr,
29         output reg rd_req,
30         output reg wr_req,
31         input rw_wait,
32         output reg [31:0] wr_data,
33         input [31:0] rd_data,
34         output reg [2:0] data_size,
35
36         /* regfile interface */
37         output reg [3:0] st_read,
38         input [31:0] st_data,
39         
40         /* Coprocessor interface */
41         output reg cp_req,
42         input cp_ack,
43         input cp_busy,
44         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
45         input [31:0] cp_read,
46         output reg [31:0] cp_write,
47         
48         /* stage inputs */
49         input inbubble,
50         input [31:0] pc,
51         input [31:0] insn,
52         input [31:0] op0,
53         input [31:0] op1,
54         input [31:0] op2,
55         input [31:0] spsr,
56         input [31:0] cpsr,
57         input cpsrup,
58         input write_reg,
59         input [3:0] write_num,
60         input [31:0] write_data,
61
62         /* outputs */
63         output reg outstall,
64         output reg outbubble,
65         output reg [31:0] outpc,
66         output reg [31:0] outinsn,
67         output reg out_write_reg = 1'b0,
68         output reg [3:0] out_write_num = 4'bxxxx,
69         output reg [31:0] out_write_data = 32'hxxxxxxxx,
70         output reg [31:0] outspsr = 32'hxxxxxxxx,
71         output reg [31:0] outcpsr = 32'hxxxxxxxx,
72         output reg outcpsrup = 1'hx
73         );
74
75         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
76         reg next_outcpsrup;
77         reg [31:0] prevaddr;
78         reg [3:0] next_regsel, cur_reg, prev_reg;
79         reg next_writeback;
80
81         reg next_outbubble;     
82         reg next_write_reg;
83         reg [3:0] next_write_num;
84         reg [31:0] next_write_data;
85
86         reg [3:0] lsr_state = 4'b0001, next_lsr_state;
87         reg [31:0] align_s1, align_s2, align_rddata;
88
89         reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
90         reg [31:0] lsrh_rddata;
91         reg [15:0] lsrh_rddata_s1;
92         reg [7:0] lsrh_rddata_s2;
93
94         reg [15:0] regs, next_regs;
95         reg [3:0] lsm_state = 4'b0001, next_lsm_state;
96         reg [5:0] offset, prev_offset, offset_sel;
97
98         reg [31:0] swp_oldval, next_swp_oldval;
99         reg [1:0] swp_state = 2'b01, next_swp_state;
100         
101         reg do_rd_data_latch;
102         reg [31:0] rd_data_latch = 32'hxxxxxxxx;
103
104         always @(posedge clk)
105         begin
106                 outpc <= pc;
107                 outinsn <= insn;
108                 outbubble <= next_outbubble;
109                 out_write_reg <= next_write_reg;
110                 out_write_num <= next_write_num;
111                 out_write_data <= next_write_data;
112                 regs <= next_regs;
113                 prev_reg <= cur_reg;
114                 if (!rw_wait)
115                         prev_offset <= offset;
116                 prev_raddr <= raddr;
117                 outcpsr <= next_outcpsr;
118                 outspsr <= spsr;
119                 outcpsrup <= next_outcpsrup;
120                 swp_state <= next_swp_state;
121                 lsm_state <= next_lsm_state;
122                 lsr_state <= next_lsr_state;
123                 lsrh_state <= next_lsrh_state;
124                 if (do_rd_data_latch)
125                         rd_data_latch <= rd_data;
126                 prevaddr <= addr;
127         end
128         
129         reg delayedflush = 0;
130         always @(posedge clk)
131                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
132                         delayedflush <= 1;
133                 else if (!outstall /* anything has been handled this time around */)
134                         delayedflush <= 0;
135         
136         /* Drive the state machines and stall. */
137         always @(*)
138         begin
139                 outstall = 1'b0;
140                 next_lsm_state = lsm_state;
141                 next_lsr_state = lsr_state;
142                 next_lsrh_state = lsrh_state;
143                 next_swp_state = swp_state;
144                 casez(insn)
145                 `DECODE_ALU_SWP: if(!inbubble) begin
146                         case(swp_state)
147                         `SWP_READING: begin
148                                 outstall = 1'b1;
149                                 if (!rw_wait)
150                                         next_swp_state = `SWP_WRITING;
151                                 $display("SWP: read stage");
152                         end
153                         `SWP_WRITING: begin
154                                 outstall = rw_wait;
155                                 if(!rw_wait)
156                                         next_swp_state = `SWP_READING;
157                                 $display("SWP: write stage");
158                         end
159                         default: begin
160                                 outstall = 1'bx;
161                                 next_swp_state = 2'bxx;
162                         end
163                         endcase
164                 end
165                 `DECODE_ALU_MULT: begin end
166                 `DECODE_ALU_HDATA_REG,
167                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
168                         case(lsrh_state)
169                         `LSRH_MEMIO: begin
170                                 outstall = rw_wait;
171                                 if(insn[21] | !insn[24]) begin
172                                         outstall = 1'b1;
173                                         if(!rw_wait)
174                                                 next_lsrh_state = `LSRH_BASEWB;
175                                 end
176                                 
177                                 if (flush) /* special case! */ begin
178                                         outstall = 1'b0;
179                                         next_lsrh_state = `LSRH_MEMIO;
180                                 end
181                                 
182                                 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
183                         end
184                         `LSRH_BASEWB: begin
185                                 outstall = 1'b1;
186                                 next_lsrh_state = `LSRH_WBFLUSH;
187                         end
188                         `LSRH_WBFLUSH: begin
189                                 outstall = 1'b0;
190                                 next_lsrh_state = `LSRH_MEMIO;
191                         end
192                         default: begin
193                                 outstall = 1'bx;
194                                 next_lsrh_state = 3'bxxx;
195                         end
196                         endcase
197                 end
198                 `DECODE_LDRSTR_UNDEFINED: begin end
199                 `DECODE_LDRSTR: if(!inbubble) begin
200                         outstall = rw_wait;
201                         case(lsr_state)
202                         `LSR_MEMIO: begin
203                                 outstall = rw_wait;
204                                 next_lsr_state = `LSR_MEMIO;
205                                 if (insn[22] /* B */ && !insn[20] /* L */) begin        /* i.e., strb */
206                                         outstall = 1'b1;
207                                         if (!rw_wait)
208                                                 next_lsr_state = `LSR_STRB_WR;
209                                 end else if (insn[21] /* W */ || !insn[24] /* P */) begin       /* writeback needed */
210                                         outstall = 1'b1;
211                                         if (!rw_wait)
212                                                 next_lsr_state = `LSR_BASEWB;
213                                 end
214                                 
215                                 if (flush) begin
216                                         outstall = 1'b0;
217                                         next_lsr_state = `LSR_MEMIO;
218                                 end
219                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
220                         end
221                         `LSR_STRB_WR: begin
222                                 outstall = 1;
223                                 if(insn[21] /* W */ | !insn[24] /* P */) begin
224                                         if(!rw_wait)
225                                                 next_lsr_state = `LSR_BASEWB;
226                                 end else if (!rw_wait)
227                                         next_lsr_state = `LSR_WBFLUSH;
228                                 $display("LDRSTR: Handling STRB");
229                         end
230                         `LSR_BASEWB: begin
231                                 outstall = 1;
232                                 next_lsr_state = `LSR_WBFLUSH;
233                         end
234                         `LSR_WBFLUSH: begin
235                                 outstall = 0;
236                                 next_lsr_state = `LSR_MEMIO;
237                         end
238                         default: begin
239                                 outstall = 1'bx;
240                                 next_lsr_state = 4'bxxxx;
241                         end
242                         endcase
243                         $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
244                 end
245                 `DECODE_LDMSTM: if(!inbubble) begin
246                         outstall = rw_wait;
247                         case(lsm_state)
248                         `LSM_SETUP: begin
249                                 outstall = 1'b1;
250                                 next_lsm_state = `LSM_MEMIO;
251                                 if (flush) begin
252                                         outstall = 1'b0;
253                                         next_lsm_state = `LSM_SETUP;
254                                 end
255                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
256                         end
257                         `LSM_MEMIO: begin
258                                 outstall = 1'b1;
259                                 if(next_regs == 16'b0) begin
260                                         next_lsm_state = `LSM_BASEWB;
261                                 end
262                                 
263                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
264                         end
265                         `LSM_BASEWB: begin
266                                 outstall = 1;
267                                 next_lsm_state = `LSM_WBFLUSH;
268                                 $display("LDMSTM: Stage 3: Writing back");
269                         end
270                         `LSM_WBFLUSH: begin
271                                 outstall = 0;
272                                 next_lsm_state = `LSM_SETUP;
273                         end
274                         default: begin
275                                 outstall = 1'bx;
276                                 next_lsm_state = 4'bxxxx;
277                         end
278                         endcase
279                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
280                 end
281                 `DECODE_LDCSTC: if(!inbubble) begin
282                         $display("WARNING: Unimplemented LDCSTC");
283                 end
284                 `DECODE_CDP: if (!inbubble) begin
285                         if (cp_busy) begin
286                                 outstall = 1;
287                         end
288                 end
289                 `DECODE_MRCMCR: if (!inbubble) begin
290                         if (cp_busy) begin
291                                 outstall = 1;
292                         end
293                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
294                 end
295                 default: begin end
296                 endcase
297         end
298
299         always @(*)
300         begin
301                 addr = prevaddr;
302                 raddr = 32'hxxxxxxxx;
303                 rd_req = 1'b0;
304                 wr_req = 1'b0;
305                 wr_data = 32'hxxxxxxxx;
306                 busaddr = 32'hxxxxxxxx;
307                 data_size = 3'bxxx;
308                 st_read = 4'hx;
309                 do_rd_data_latch = 0;
310                 next_write_reg = write_reg;
311                 next_write_num = write_num;
312                 next_write_data = write_data;
313                 next_outbubble = inbubble;
314                 next_regs = regs;
315                 cp_req = 1'b0;
316                 cp_rnw = 1'bx;
317                 cp_write = 32'hxxxxxxxx;
318                 offset = prev_offset;
319                 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
320                 next_outcpsrup = cpsrup;
321                 lsrh_rddata = 32'hxxxxxxxx;
322                 lsrh_rddata_s1 = 16'hxxxx;
323                 lsrh_rddata_s2 = 8'hxx;
324                 next_swp_oldval = swp_oldval;
325                 cur_reg = prev_reg;
326
327                 /* XXX shit not given about endianness */
328                 casez(insn)
329                 `DECODE_ALU_SWP: if(!inbubble) begin
330                         next_outbubble = rw_wait;
331                         busaddr = {op0[31:2], 2'b0};
332                         data_size = insn[22] ? 3'b001 : 3'b100;
333                         case(swp_state)
334                         `SWP_READING: begin
335                                 rd_req = 1'b1;
336                                 if(!rw_wait) begin
337                                         next_swp_oldval = rd_data;
338                                 end
339                         end
340                         `SWP_WRITING: begin
341                                 wr_req = 1'b1;
342                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
343                                 next_write_reg = 1'b1;
344                                 next_write_num = insn[15:12];
345                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
346                         end
347                         default: begin end
348                         endcase
349                 end
350                 `DECODE_ALU_MULT: begin end
351                 `DECODE_ALU_HDATA_REG,
352                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
353                         next_outbubble = rw_wait;
354                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
355                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
356                         busaddr = raddr;
357                         /* rotate to correct position */
358                         case(insn[6:5])
359                         2'b01: begin /* unsigned half */
360                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
361                                 data_size = 3'b010;
362                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
363                         end
364                         2'b10: begin /* signed byte */
365                                 wr_data = {4{op2[7:0]}};
366                                 data_size = 3'b001;
367                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
368                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
369                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
370                         end
371                         2'b11: begin /* signed half */
372                                 wr_data = {2{op2[15:0]}};
373                                 data_size = 3'b010;
374                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
375                         end
376                         default: begin
377                                 wr_data = 32'hxxxxxxxx;
378                                 data_size = 3'bxxx;
379                                 lsrh_rddata = 32'hxxxxxxxx;
380                         end
381                         endcase
382
383                         case(lsrh_state)
384                         `LSRH_MEMIO: begin
385                                 rd_req = insn[20];
386                                 wr_req = ~insn[20];
387                                 next_write_num = insn[15:12];
388                                 next_write_data = lsrh_rddata;
389                                 if(insn[20]) begin
390                                         next_write_reg = 1'b1;
391                                 end
392                         end
393                         `LSRH_BASEWB: begin
394                                 next_outbubble = 1'b0;
395                                 next_write_reg = 1'b1;
396                                 next_write_num = insn[19:16];
397                                 next_write_data = addr;
398                         end
399                         `LSRH_WBFLUSH: begin
400                         end
401                         default: begin end
402                         endcase
403                 end
404                 `DECODE_LDRSTR_UNDEFINED: begin end
405                 `DECODE_LDRSTR: if(!inbubble) begin
406                         next_outbubble = rw_wait;
407                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
408                         raddr = insn[24] ? addr : op0; /* pre/post increment */
409                         busaddr = raddr;
410                         /* rotate to correct position */
411                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
412                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
413                         /* select byte or word */
414                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
415                         wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
416                         data_size = insn[22] ? 3'b001 : 3'b100;
417                         case(lsr_state)
418                         `LSR_MEMIO: begin
419                                 rd_req = insn[20] /* L */ || insn[22] /* B */;
420                                 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
421                                 next_write_reg = insn[20] /* L */;
422                                 next_write_num = insn[15:12];
423                                 if(insn[20] /* L */) begin
424                                         next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
425                                 end
426                                 if (insn[22] /* B */ && !insn[20] /* L */) begin
427                                         do_rd_data_latch = 1;
428                                 end
429                         end
430                         `LSR_STRB_WR: begin
431                                 rd_req = 0;
432                                 wr_req = 1;
433                                 next_write_reg = 0;
434                                 case (busaddr[1:0])
435                                 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
436                                 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
437                                 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
438                                 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
439                                 endcase
440                         end
441                         `LSR_BASEWB: begin
442                                 rd_req = 0;
443                                 wr_req = 0;
444                                 next_outbubble = 0;
445                                 next_write_reg = 1'b1;
446                                 next_write_num = insn[19:16];
447                                 next_write_data = addr;
448                         end
449                         `LSR_WBFLUSH: begin
450                                 rd_req = 0;
451                                 wr_req = 0;
452                         end
453                         default: begin end
454                         endcase
455                 end
456                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
457                 `DECODE_LDMSTM: if(!inbubble) begin
458                         next_outbubble = rw_wait;
459                         data_size = 3'b100;
460                         case(lsm_state)
461                         `LSM_SETUP: begin
462 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
463                                 /** verilator can suck my dick */
464                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
465                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
466                                 offset = 6'b0;
467                         end
468                         `LSM_MEMIO: begin
469                                 rd_req = insn[20];
470                                 wr_req = ~insn[20];
471                                 casez(regs)
472                                 16'b???????????????1: begin
473                                         cur_reg = 4'h0;
474                                         next_regs = {regs[15:1], 1'b0};
475                                 end
476                                 16'b??????????????10: begin
477                                         cur_reg = 4'h1;
478                                         next_regs = {regs[15:2], 2'b0};
479                                 end
480                                 16'b?????????????100: begin
481                                         cur_reg = 4'h2;
482                                         next_regs = {regs[15:3], 3'b0};
483                                 end
484                                 16'b????????????1000: begin
485                                         cur_reg = 4'h3;
486                                         next_regs = {regs[15:4], 4'b0};
487                                 end
488                                 16'b???????????10000: begin
489                                         cur_reg = 4'h4;
490                                         next_regs = {regs[15:5], 5'b0};
491                                 end
492                                 16'b??????????100000: begin
493                                         cur_reg = 4'h5;
494                                         next_regs = {regs[15:6], 6'b0};
495                                 end
496                                 16'b?????????1000000: begin
497                                         cur_reg = 4'h6;
498                                         next_regs = {regs[15:7], 7'b0};
499                                 end
500                                 16'b????????10000000: begin
501                                         cur_reg = 4'h7;
502                                         next_regs = {regs[15:8], 8'b0};
503                                 end
504                                 16'b???????100000000: begin
505                                         cur_reg = 4'h8;
506                                         next_regs = {regs[15:9], 9'b0};
507                                 end
508                                 16'b??????1000000000: begin
509                                         cur_reg = 4'h9;
510                                         next_regs = {regs[15:10], 10'b0};
511                                 end
512                                 16'b?????10000000000: begin
513                                         cur_reg = 4'hA;
514                                         next_regs = {regs[15:11], 11'b0};
515                                 end
516                                 16'b????100000000000: begin
517                                         cur_reg = 4'hB;
518                                         next_regs = {regs[15:12], 12'b0};
519                                 end
520                                 16'b???1000000000000: begin
521                                         cur_reg = 4'hC;
522                                         next_regs = {regs[15:13], 13'b0};
523                                 end
524                                 16'b??10000000000000: begin
525                                         cur_reg = 4'hD;
526                                         next_regs = {regs[15:14], 14'b0};
527                                 end
528                                 16'b?100000000000000: begin
529                                         cur_reg = 4'hE;
530                                         next_regs = {regs[15], 15'b0};
531                                 end
532                                 16'b1000000000000000: begin
533                                         cur_reg = 4'hF;
534                                         next_regs = 16'b0;
535                                 end
536                                 default: begin
537                                         cur_reg = 4'hx;
538                                         next_regs = 16'b0;
539                                 end
540                                 endcase
541                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
542                                 if(cur_reg == 4'hF && insn[22]) begin
543                                         next_outcpsr = spsr;
544                                         next_outcpsrup = 1;
545                                 end
546
547                                 offset = prev_offset + 6'h4;
548                                 offset_sel = insn[24] ? offset : prev_offset;
549                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
550                                 if(insn[20]) begin
551                                         next_write_reg = !rw_wait;
552                                         next_write_num = cur_reg;
553                                         next_write_data = rd_data;
554                                 end
555                                 if (rw_wait) begin
556                                         next_regs = regs;
557                                         cur_reg = prev_reg;     /* whoops, do this one again */
558                                 end
559
560                                 st_read = cur_reg;
561                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
562                                 busaddr = raddr;
563                         end
564                         `LSM_BASEWB: begin
565                                 next_outbubble = 0;
566                                 next_write_reg = insn[21] /* writeback */;
567                                 next_write_num = insn[19:16];
568                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
569                         end
570                         `LSM_WBFLUSH: begin end
571                         default: $stop;
572                         endcase
573                 end
574                 `DECODE_LDCSTC: begin end
575                 `DECODE_CDP: if(!inbubble) begin
576                         cp_req = 1;
577                         if (cp_busy) begin
578                                 next_outbubble = 1;
579                         end
580                         if (!cp_ack) begin
581                                 /* XXX undefined instruction trap */
582                                 $display("WARNING: Possible CDP undefined instruction");
583                         end
584                 end
585                 `DECODE_MRCMCR: if(!inbubble) begin
586                         cp_req = 1;
587                         cp_rnw = insn[20] /* L */;
588                         if (insn[20] == 0 /* store to coprocessor */)
589                                 cp_write = op0;
590                         else begin
591                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
592                                         next_write_reg = 1'b1;
593                                         next_write_num = insn[15:12];
594                                         next_write_data = cp_read;
595                                 end else begin
596                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
597                                         next_outcpsrup = 1;
598                                 end
599                         end
600                         if (cp_busy) begin
601                                 next_outbubble = 1;
602                         end
603                         if (!cp_ack) begin
604                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
605                         end
606                 end
607                 default: begin end
608                 endcase
609                 
610                 if ((flush || delayedflush) && !outstall)
611                         next_outbubble = 1'b1;
612         end
613 endmodule
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