Dual boot ROM support, and the first proof that cellular ram works!
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg rdlatch = 0;
10         reg [7:0] odata;
11
12         // synthesis attribute ram_style of rom is block
13         reg [7:0] rom [1023:0];
14         initial $readmemh("rom.hex", rom);
15
16         wire decode = address[15:13] == 0;
17         always @(posedge clk) begin
18                 rdlatch <= rd && decode;
19                 odata <= rom[address[10:0]];
20         end
21         assign data = rdlatch ? odata : 8'bzzzzzzzz;
22 endmodule
23
24 module BootstrapROM(
25         input [15:0] address,
26         inout [7:0] data,
27         input clk,
28         input wr, rd);
29
30         reg rdlatch = 0;
31         reg [7:0] addrlatch = 0;
32         reg romno = 0, romnotmp = 0;
33         reg [7:0] brom0 [255:0];
34         reg [7:0] brom1 [255:0];
35         
36         initial $readmemh("fpgaboot.hex", brom0);
37         initial $readmemh("gbboot.hex", brom1);
38
39         wire decode = address[15:8] == 0;
40         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
41         always @(posedge clk) begin
42                 rdlatch <= rd && decode;
43                 addrlatch <= address[7:0];
44                 if (wr && decode) romnotmp <= data[0];
45                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
46         end
47         assign data = rdlatch ? odata : 8'bzzzzzzzz;
48 endmodule
49
50 module MiniRAM(
51         input [15:0] address,
52         inout [7:0] data,
53         input clk,
54         input wr, rd);
55         
56         reg [7:0] ram [127:0];
57         
58         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
59         reg rdlatch = 0;
60         reg [7:0] odata;
61         assign data = rdlatch ? odata : 8'bzzzzzzzz;
62         
63         always @(posedge clk)
64         begin
65                 rdlatch <= rd && decode;
66                 if (decode)             // This has to go this way. The only way XST knows how to do
67                 begin                   // block ram is chip select, write enable, and always
68                         if (wr)         // reading. "else if rd" does not cut it ...
69                                 ram[address[6:0]] <= data;
70                         odata <= ram[address[6:0]];
71                 end
72         end
73 endmodule
74
75 module CellularRAM(
76         input clk,
77         input [15:0] address,
78         inout [7:0] data,
79         input wr, rd,
80         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
81         output wire [22:0] cr_A,
82         inout [15:0] cr_DQ);
83         
84         parameter ADDR_PROGADDRH = 16'hFF60;
85         parameter ADDR_PROGADDRM = 16'hFF61;
86         parameter ADDR_PROGADDRL = 16'hFF62;
87         parameter ADDR_PROGDATA = 16'hFF63;
88         
89         reg rdlatch = 0, wrlatch = 0;
90         reg [15:0] addrlatch = 0;
91         reg [7:0] datalatch = 0;
92         
93         reg [7:0] progaddrh, progaddrm, progaddrl;
94         
95         assign cr_nADV = 0;     /* Addresses are always valid! :D */
96         assign cr_nCE = 0;      /* The chip is enabled */
97         assign cr_nLB = 0;      /* Lower byte is enabled */
98         assign cr_nUB = 0;      /* Upper byte is enabled */
99         assign cr_CRE = 0;      /* Data writes, not config */
100         assign cr_CLK = 0;      /* Clock? I think not! */
101         
102         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
103         
104         assign cr_nOE = decode ? ~rdlatch : 1;
105         assign cr_nWE = decode ? ~wrlatch : 1;
106         
107         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
108         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
109                         (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
110                         (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
111                         23'b0;
112         
113         reg [7:0] regbuf;
114         
115         always @(posedge clk) begin
116                 case (address)
117                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
118                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
119                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
120                 endcase
121                 rdlatch <= rd;
122                 wrlatch <= wr;
123                 addrlatch <= address;
124                 datalatch <= data;
125         end
126         
127         assign data = (rdlatch && decode) ?
128                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
129                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
130                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
131                                 cr_DQ
132                         : 8'bzzzzzzzz;
133 endmodule
134
135 module InternalRAM(
136         input [15:0] address,
137         inout [7:0] data,
138         input clk,
139         input wr, rd);
140         
141         // synthesis attribute ram_style of ram is block
142         reg [7:0] ram [8191:0];
143         
144         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
145         reg [7:0] odata;
146         reg rdlatch = 0;
147         assign data = rdlatch ? odata : 8'bzzzzzzzz;
148         
149         always @(posedge clk)
150         begin
151                 rdlatch <= rd && decode;
152                 if (decode)             // This has to go this way. The only way XST knows how to do
153                 begin                   // block ram is chip select, write enable, and always
154                         if (wr)         // reading. "else if rd" does not cut it ...
155                                 ram[address[12:0]] <= data;
156                         odata <= ram[address[12:0]];
157                 end
158         end
159 endmodule
160
161 module Switches(
162         input [15:0] address,
163         inout [7:0] data,
164         input clk,
165         input wr, rd,
166         input [7:0] switches,
167         output reg [7:0] ledout = 0);
168         
169         wire decode = address == 16'hFF51;
170         reg [7:0] odata;
171         reg rdlatch = 0;
172         assign data = rdlatch ? odata : 8'bzzzzzzzz;
173         
174         always @(posedge clk)
175         begin
176                 rdlatch <= rd && decode;
177                 if (decode && rd)
178                         odata <= switches;
179                 else if (decode && wr)
180                         ledout <= data;
181         end
182 endmodule
183
184 `ifdef isim
185 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
186 endmodule
187 `endif
188
189 module CoreTop(
190 `ifdef isim
191         output reg vgaclk = 0,
192         output reg clk = 0,
193 `else
194         input xtal,
195         input [7:0] switches,
196         input [3:0] buttons,
197         output wire [7:0] leds,
198         output serio,
199         output wire [3:0] digits,
200         output wire [7:0] seven,
201         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
202         output wire [22:0] cr_A,
203         inout [15:0] cr_DQ,
204 `endif
205         output wire hs, vs,
206         output wire [2:0] r, g,
207         output wire [1:0] b,
208         output wire soundl, soundr);
209
210 `ifdef isim
211         always #62 clk <= ~clk;
212         always #100 vgaclk <= ~vgaclk;
213         
214         Dumpable dump(r,g,b,hs,vs,vgaclk);
215         
216         wire [7:0] leds;
217         wire serio;
218         wire [3:0] digits;
219         wire [7:0] seven;
220         wire [7:0] switches = 8'b0;
221         wire [3:0] buttons = 4'b0;
222 `else   
223         wire xtalb, clk, vgaclk;
224         IBUFG iclkbuf(.O(xtalb), .I(xtal));
225         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
226         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
227 `endif
228
229         wire [15:0] addr [1:0];
230         wire [7:0] data [1:0];
231         wire wr [1:0], rd [1:0];
232         
233         wire irq, tmrirq, lcdcirq, vblankirq;
234         wire [7:0] jaddr;
235         wire [1:0] state;
236         
237         GBZ80Core core(
238                 .clk(clk),
239                 .bus0address(addr[0]),
240                 .bus0data(data[0]),
241                 .bus0wr(wr[0]),
242                 .bus0rd(rd[0]),
243                 .bus1address(addr[1]),
244                 .bus1data(data[1]),
245                 .bus1wr(wr[1]),
246                 .bus1rd(rd[1]),
247                 .irq(irq),
248                 .jaddr(jaddr),
249                 .state(state));
250         
251         BootstrapROM brom(
252                 .address(addr[1]),
253                 .data(data[1]),
254                 .clk(clk),
255                 .wr(wr[1]),
256                 .rd(rd[1]));
257         
258 `ifdef isim
259         ROM rom(
260                 .address(addr[0]),
261                 .data(data[0]),
262                 .clk(clk),
263                 .wr(wr[0]),
264                 .rd(rd[0]));
265 `else
266         CellularRAM cellram(
267                 .address(addr[0]),
268                 .data(data[0]),
269                 .clk(clk),
270                 .wr(wr[0]),
271                 .rd(rd[0]),
272                 .cr_nADV(cr_nADV),
273                 .cr_nCE(cr_nCE),
274                 .cr_nOE(cr_nOE),
275                 .cr_nWE(cr_nWE),
276                 .cr_CRE(cr_CRE),
277                 .cr_nLB(cr_nLB),
278                 .cr_nUB(cr_nUB),
279                 .cr_CLK(cr_CLK),
280                 .cr_A(cr_A),
281                 .cr_DQ(cr_DQ));
282 `endif
283         
284         wire lcdhs, lcdvs, lcdclk;
285         wire [2:0] lcdr, lcdg;
286         wire [1:0] lcdb;
287         
288         LCDC lcdc(
289                 .clk(clk),
290                 .addr(addr[0]),
291                 .data(data[0]),
292                 .wr(wr[0]),
293                 .rd(rd[0]),
294                 .lcdcirq(lcdcirq),
295                 .vblankirq(vblankirq),
296                 .lcdclk(lcdclk),
297                 .lcdhs(lcdhs),
298                 .lcdvs(lcdvs),
299                 .lcdr(lcdr),
300                 .lcdg(lcdg),
301                 .lcdb(lcdb));
302         
303         Framebuffer fb(
304                 .lcdclk(lcdclk),
305                 .lcdhs(lcdhs),
306                 .lcdvs(lcdvs),
307                 .lcdr(lcdr),
308                 .lcdg(lcdg),
309                 .lcdb(lcdb),
310                 .vgaclk(vgaclk),
311                 .vgahs(hs),
312                 .vgavs(vs),
313                 .vgar(r),
314                 .vgag(g),
315                 .vgab(b));
316         
317         AddrMon amon(
318                 .clk(clk), 
319                 .addr(addr[0]),
320                 .digit(digits), 
321                 .out(seven),
322                 .freeze(buttons[0]),
323                 .periods(
324                         (state == 2'b00) ? 4'b0010 :
325                         (state == 2'b01) ? 4'b0001 :
326                         (state == 2'b10) ? 4'b1000 :
327                                            4'b0100) );
328          
329         Switches sw(
330                 .clk(clk),
331                 .address(addr[0]),
332                 .data(data[0]),
333                 .wr(wr[0]),
334                 .rd(rd[0]),
335                 .ledout(leds),
336                 .switches(switches)
337                 );
338
339         UART nouart (   /* no u */
340                 .clk(clk),
341                 .addr(addr[0]),
342                 .data(data[0]),
343                 .wr(wr[0]),
344                 .rd(rd[0]),
345                 .serial(serio)
346                 );
347
348         InternalRAM ram(
349                 .clk(clk),
350                 .address(addr[0]),
351                 .data(data[0]),
352                 .wr(wr[0]),
353                 .rd(rd[0])
354                 );
355         
356         MiniRAM mram(
357                 .clk(clk),
358                 .address(addr[1]),
359                 .data(data[1]),
360                 .wr(wr[1]),
361                 .rd(rd[1])
362                 );
363
364         Timer tmr(
365                 .clk(clk),
366                 .addr(addr[0]),
367                 .data(data[0]),
368                 .wr(wr[0]),
369                 .rd(rd[0]),
370                 .irq(tmrirq)
371                 );
372         
373         Interrupt intr(
374                 .clk(clk),
375                 .addr(addr[0]),
376                 .data(data[0]),
377                 .wr(wr[0]),
378                 .rd(rd[0]),
379                 .vblank(vblankirq),
380                 .lcdc(lcdcirq),
381                 .tovf(tmrirq),
382                 .serial(1'b0),
383                 .buttons(1'b0),
384                 .master(irq),
385                 .jaddr(jaddr));
386         
387         Soundcore sound(
388                 .core_clk(clk),
389                 .addr(addr[0]),
390                 .data(data[0]),
391                 .rd(rd[0]),
392                 .wr(wr[0]),
393                 .snd_data_l(soundl),
394                 .snd_data_r(soundr));
395 endmodule
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