Memory: Remove magic numbers from state machines.
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         input flush,
8
9         /* bus interface */
10         output reg [31:0] busaddr,
11         output reg rd_req,
12         output reg wr_req,
13         input rw_wait,
14         output reg [31:0] wr_data,
15         input [31:0] rd_data,
16         output reg [2:0] data_size,
17
18         /* regfile interface */
19         output reg [3:0] st_read,
20         input [31:0] st_data,
21         
22         /* Coprocessor interface */
23         output reg cp_req,
24         input cp_ack,
25         input cp_busy,
26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
27         input [31:0] cp_read,
28         output reg [31:0] cp_write,
29         
30         /* stage inputs */
31         input inbubble,
32         input [31:0] pc,
33         input [31:0] insn,
34         input [31:0] op0,
35         input [31:0] op1,
36         input [31:0] op2,
37         input [31:0] spsr,
38         input [31:0] cpsr,
39         input cpsrup,
40         input write_reg,
41         input [3:0] write_num,
42         input [31:0] write_data,
43
44         /* outputs */
45         output reg outstall,
46         output reg outbubble,
47         output reg [31:0] outpc,
48         output reg [31:0] outinsn,
49         output reg out_write_reg = 1'b0,
50         output reg [3:0] out_write_num = 4'bxxxx,
51         output reg [31:0] out_write_data = 32'hxxxxxxxx,
52         output reg [31:0] outspsr = 32'hxxxxxxxx,
53         output reg [31:0] outcpsr = 32'hxxxxxxxx,
54         output reg outcpsrup = 1'hx
55         );
56
57         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
58         reg next_outcpsrup;
59         reg [31:0] prevaddr;
60         reg [3:0] next_regsel, cur_reg, prev_reg;
61         reg next_writeback;
62
63         reg next_outbubble;     
64         reg next_write_reg;
65         reg [3:0] next_write_num;
66         reg [31:0] next_write_data;
67
68         reg [3:0] lsr_state = 4'b0001, next_lsr_state;
69         reg [31:0] align_s1, align_s2, align_rddata;
70
71         reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
72         reg [31:0] lsrh_rddata;
73         reg [15:0] lsrh_rddata_s1;
74         reg [7:0] lsrh_rddata_s2;
75
76         reg [15:0] regs, next_regs;
77         reg [3:0] lsm_state = 4'b0001, next_lsm_state;
78         reg [5:0] offset, prev_offset, offset_sel;
79
80         reg [31:0] swp_oldval, next_swp_oldval;
81         reg [1:0] swp_state = 2'b01, next_swp_state;
82         
83         reg do_rd_data_latch;
84         reg [31:0] rd_data_latch = 32'hxxxxxxxx;
85
86         always @(posedge clk)
87         begin
88                 outpc <= pc;
89                 outinsn <= insn;
90                 outbubble <= next_outbubble;
91                 out_write_reg <= next_write_reg;
92                 out_write_num <= next_write_num;
93                 out_write_data <= next_write_data;
94                 regs <= next_regs;
95                 prev_reg <= cur_reg;
96                 if (!rw_wait)
97                         prev_offset <= offset;
98                 prev_raddr <= raddr;
99                 outcpsr <= next_outcpsr;
100                 outspsr <= spsr;
101                 outcpsrup <= next_outcpsrup;
102                 swp_state <= next_swp_state;
103                 lsm_state <= next_lsm_state;
104                 lsr_state <= next_lsr_state;
105                 lsrh_state <= next_lsrh_state;
106                 if (do_rd_data_latch)
107                         rd_data_latch <= rd_data;
108                 prevaddr <= addr;
109         end
110         
111         reg delayedflush = 0;
112         always @(posedge clk)
113                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
114                         delayedflush <= 1;
115                 else if (!outstall /* anything has been handled this time around */)
116                         delayedflush <= 0;
117
118         always @(*)
119         begin
120                 addr = prevaddr;
121                 raddr = 32'hxxxxxxxx;
122                 rd_req = 1'b0;
123                 wr_req = 1'b0;
124                 wr_data = 32'hxxxxxxxx;
125                 busaddr = 32'hxxxxxxxx;
126                 data_size = 3'bxxx;
127                 outstall = 1'b0;
128                 st_read = 4'hx;
129                 do_rd_data_latch = 0;
130                 next_write_reg = write_reg;
131                 next_write_num = write_num;
132                 next_write_data = write_data;
133                 next_outbubble = inbubble;
134                 next_regs = regs;
135                 cp_req = 1'b0;
136                 cp_rnw = 1'bx;
137                 cp_write = 32'hxxxxxxxx;
138                 offset = prev_offset;
139                 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
140                 next_outcpsrup = cpsrup;
141                 lsrh_rddata = 32'hxxxxxxxx;
142                 lsrh_rddata_s1 = 16'hxxxx;
143                 lsrh_rddata_s2 = 8'hxx;
144                 next_lsm_state = lsm_state;
145                 next_lsr_state = lsr_state;
146                 next_lsrh_state = lsrh_state;
147                 next_swp_oldval = swp_oldval;
148                 next_swp_state = swp_state;
149                 cur_reg = prev_reg;
150
151 `define SWP_READING 2'b01
152 `define SWP_WRITING 2'b10
153
154 `define LSRH_MEMIO      3'b001
155 `define LSRH_BASEWB     3'b010
156 `define LSRH_WBFLUSH    3'b100
157
158 `define LSR_MEMIO       4'b0001
159 `define LSR_STRB_WR     4'b0010
160 `define LSR_BASEWB      4'b0100
161 `define LSR_WBFLUSH     4'b1000
162
163 `define LSM_SETUP       4'b0001
164 `define LSM_MEMIO       4'b0010
165 `define LSM_BASEWB      4'b0100
166 `define LSM_WBFLUSH     4'b1000
167
168                 /* XXX shit not given about endianness */
169                 casez(insn)
170                 `DECODE_ALU_SWP: if(!inbubble) begin
171                         outstall = rw_wait;
172                         next_outbubble = rw_wait;
173                         busaddr = {op0[31:2], 2'b0};
174                         data_size = insn[22] ? 3'b001 : 3'b100;
175                         case(swp_state)
176                         `SWP_READING: begin
177                                 rd_req = 1'b1;
178                                 outstall = 1'b1;
179                                 if(!rw_wait) begin
180                                         next_swp_state = `SWP_WRITING;
181                                         next_swp_oldval = rd_data;
182                                 end
183                                 $display("SWP: read stage");
184                         end
185                         `SWP_WRITING: begin
186                                 wr_req = 1'b1;
187                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
188                                 next_write_reg = 1'b1;
189                                 next_write_num = insn[15:12];
190                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
191                                 if(!rw_wait)
192                                         next_swp_state = `SWP_READING;
193                                 $display("SWP: write stage");
194                         end
195                         default: begin end
196                         endcase
197                 end
198                 `DECODE_ALU_MULT: begin end
199                 `DECODE_ALU_HDATA_REG,
200                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
201                         next_outbubble = rw_wait;
202                         outstall = rw_wait;
203                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
204                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
205                         busaddr = raddr;
206                         /* rotate to correct position */
207                         case(insn[6:5])
208                         2'b01: begin /* unsigned half */
209                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
210                                 data_size = 3'b010;
211                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
212                         end
213                         2'b10: begin /* signed byte */
214                                 wr_data = {4{op2[7:0]}};
215                                 data_size = 3'b001;
216                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
217                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
218                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
219                         end
220                         2'b11: begin /* signed half */
221                                 wr_data = {2{op2[15:0]}};
222                                 data_size = 3'b010;
223                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
224                         end
225                         default: begin
226                                 wr_data = 32'hxxxxxxxx;
227                                 data_size = 3'bxxx;
228                                 lsrh_rddata = 32'hxxxxxxxx;
229                         end
230                         endcase
231
232                         case(lsrh_state)
233                         `LSRH_MEMIO: begin
234                                 rd_req = insn[20];
235                                 wr_req = ~insn[20];
236                                 next_write_num = insn[15:12];
237                                 next_write_data = lsrh_rddata;
238                                 if(insn[20]) begin
239                                         next_write_reg = 1'b1;
240                                 end
241                                 if(insn[21] | !insn[24]) begin
242                                         outstall = 1'b1;
243                                         if(!rw_wait)
244                                                 next_lsrh_state = `LSRH_BASEWB;
245                                 end
246                                 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
247                         end
248                         `LSRH_BASEWB: begin
249                                 next_outbubble = 1'b0;
250                                 next_write_reg = 1'b1;
251                                 next_write_num = insn[19:16];
252                                 next_write_data = addr;
253                                 next_lsrh_state = `LSRH_WBFLUSH;
254                         end
255                         `LSRH_WBFLUSH: begin
256                                 outstall = 0;
257                                 next_lsrh_state = `LSRH_MEMIO;
258                         end
259                         default: begin end
260                         endcase
261                         
262                         if ((lsrh_state == `LSRH_MEMIO) && flush) begin /* Reject it. */
263                                 outstall = 1'b0;
264                                 next_lsrh_state = `LSRH_MEMIO;
265                         end
266                 end
267                 `DECODE_LDRSTR_UNDEFINED: begin end
268                 `DECODE_LDRSTR: if(!inbubble) begin
269                         next_outbubble = rw_wait;
270                         outstall = rw_wait;
271                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
272                         raddr = insn[24] ? addr : op0; /* pre/post increment */
273                         busaddr = raddr;
274                         /* rotate to correct position */
275                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
276                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
277                         /* select byte or word */
278                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
279                         wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
280                         data_size = insn[22] ? 3'b001 : 3'b100;
281                         case(lsr_state)
282
283                         `LSR_MEMIO: begin
284                                 rd_req = insn[20] /* L */ || insn[22] /* B */;
285                                 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
286                                 next_write_reg = insn[20] /* L */;
287                                 next_write_num = insn[15:12];
288                                 if(insn[20] /* L */) begin
289                                         next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
290                                 end
291                                 if (insn[22] /* B */ && !insn[20] /* L */) begin
292                                         do_rd_data_latch = 1;
293                                         outstall = 1'b1;
294                                         if (!rw_wait)
295                                                 next_lsr_state = `LSR_STRB_WR;
296                                 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
297                                         outstall = 1'b1;
298                                         if(!rw_wait)
299                                                 next_lsr_state = `LSR_BASEWB;
300                                 end
301                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
302                         end
303                         `LSR_STRB_WR: begin
304                                 $display("LDRSTR: Handling STRB");
305                                 outstall = 1;
306                                 rd_req = 0;
307                                 wr_req = 1;
308                                 next_write_reg = 0;
309                                 case (busaddr[1:0])
310                                 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
311                                 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
312                                 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
313                                 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
314                                 endcase
315                                 if(insn[21] /* W */ | !insn[24] /* P */) begin
316                                         if(!rw_wait)
317                                                 next_lsr_state = `LSR_BASEWB;
318                                 end else if (!rw_wait)
319                                         next_lsr_state = `LSR_WBFLUSH;
320                         end
321                         `LSR_BASEWB: begin
322                                 outstall = 1;
323                                 rd_req = 0;
324                                 wr_req= 0;
325                                 next_outbubble = 0;
326                                 next_write_reg = 1'b1;
327                                 next_write_num = insn[19:16];
328                                 next_write_data = addr;
329                                 next_lsr_state = `LSR_WBFLUSH;
330                         end
331                         `LSR_WBFLUSH: begin
332                                 rd_req = 0;
333                                 wr_req= 0;
334                                 outstall = 0;
335                                 next_lsr_state = `LSR_MEMIO;
336                         end
337                         default: begin end
338                         endcase
339                         
340                         if ((lsr_state == `LSR_MEMIO) && flush) begin   /* Reject it. */
341                                 outstall = 1'b0;
342                                 next_lsr_state = `LSR_MEMIO;
343                         end
344                 end
345                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
346                 `DECODE_LDMSTM: if(!inbubble) begin
347                         outstall = rw_wait;
348                         next_outbubble = rw_wait;
349                         data_size = 3'b100;
350                         case(lsm_state)
351                         `LSM_SETUP: begin
352 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
353                                 /** verilator can suck my dick */
354                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
355                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
356                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
357                                 offset = 6'b0;
358                                 outstall = 1'b1;
359                                 next_lsm_state = `LSM_MEMIO;
360                         end
361                         4'b0010: begin
362                                 rd_req = insn[20];
363                                 wr_req = ~insn[20];
364                                 casez(regs)
365                                 16'b???????????????1: begin
366                                         cur_reg = 4'h0;
367                                         next_regs = {regs[15:1], 1'b0};
368                                 end
369                                 16'b??????????????10: begin
370                                         cur_reg = 4'h1;
371                                         next_regs = {regs[15:2], 2'b0};
372                                 end
373                                 16'b?????????????100: begin
374                                         cur_reg = 4'h2;
375                                         next_regs = {regs[15:3], 3'b0};
376                                 end
377                                 16'b????????????1000: begin
378                                         cur_reg = 4'h3;
379                                         next_regs = {regs[15:4], 4'b0};
380                                 end
381                                 16'b???????????10000: begin
382                                         cur_reg = 4'h4;
383                                         next_regs = {regs[15:5], 5'b0};
384                                 end
385                                 16'b??????????100000: begin
386                                         cur_reg = 4'h5;
387                                         next_regs = {regs[15:6], 6'b0};
388                                 end
389                                 16'b?????????1000000: begin
390                                         cur_reg = 4'h6;
391                                         next_regs = {regs[15:7], 7'b0};
392                                 end
393                                 16'b????????10000000: begin
394                                         cur_reg = 4'h7;
395                                         next_regs = {regs[15:8], 8'b0};
396                                 end
397                                 16'b???????100000000: begin
398                                         cur_reg = 4'h8;
399                                         next_regs = {regs[15:9], 9'b0};
400                                 end
401                                 16'b??????1000000000: begin
402                                         cur_reg = 4'h9;
403                                         next_regs = {regs[15:10], 10'b0};
404                                 end
405                                 16'b?????10000000000: begin
406                                         cur_reg = 4'hA;
407                                         next_regs = {regs[15:11], 11'b0};
408                                 end
409                                 16'b????100000000000: begin
410                                         cur_reg = 4'hB;
411                                         next_regs = {regs[15:12], 12'b0};
412                                 end
413                                 16'b???1000000000000: begin
414                                         cur_reg = 4'hC;
415                                         next_regs = {regs[15:13], 13'b0};
416                                 end
417                                 16'b??10000000000000: begin
418                                         cur_reg = 4'hD;
419                                         next_regs = {regs[15:14], 14'b0};
420                                 end
421                                 16'b?100000000000000: begin
422                                         cur_reg = 4'hE;
423                                         next_regs = {regs[15], 15'b0};
424                                 end
425                                 16'b1000000000000000: begin
426                                         cur_reg = 4'hF;
427                                         next_regs = 16'b0;
428                                 end
429                                 default: begin
430                                         cur_reg = 4'hx;
431                                         next_regs = 16'b0;
432                                 end
433                                 endcase
434                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
435                                 if(cur_reg == 4'hF && insn[22]) begin
436                                         next_outcpsr = spsr;
437                                         next_outcpsrup = 1;
438                                 end
439
440                                 offset = prev_offset + 6'h4;
441                                 offset_sel = insn[24] ? offset : prev_offset;
442                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
443                                 if(insn[20]) begin
444                                         next_write_reg = !rw_wait;
445                                         next_write_num = cur_reg;
446                                         next_write_data = rd_data;
447                                 end
448                                 if (rw_wait) begin
449                                         next_regs = regs;
450                                         cur_reg = prev_reg;     /* whoops, do this one again */
451                                 end
452
453                                 st_read = cur_reg;
454                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
455                                 busaddr = raddr;
456                                 
457                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
458
459                                 outstall = 1'b1;
460
461                                 if(next_regs == 16'b0) begin
462                                         next_lsm_state = `LSM_BASEWB;
463                                 end
464                         end
465                         `LSM_BASEWB: begin
466                                 outstall = 1;
467                                 next_outbubble = 0;
468                                 next_write_reg = insn[21] /* writeback */;
469                                 next_write_num = insn[19:16];
470                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
471                                 next_lsm_state = `LSM_WBFLUSH;
472                                 $display("LDMSTM: Stage 3: Writing back");
473                         end
474                         `LSM_WBFLUSH: begin
475                                 outstall = 0;
476                                 next_lsm_state = `LSM_SETUP;
477                         end
478                         default: $stop;
479                         endcase
480                         if ((lsm_state == `LSM_SETUP) && flush) begin   /* Reject it. */
481                                 outstall = 1'b0;
482                                 next_lsm_state = `LSM_SETUP;
483                         end
484                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
485                 end
486                 `DECODE_LDCSTC: if(!inbubble) begin
487                         $display("WARNING: Unimplemented LDCSTC");
488                 end
489                 `DECODE_CDP: if(!inbubble) begin
490                         cp_req = 1;
491                         if (cp_busy) begin
492                                 outstall = 1;
493                                 next_outbubble = 1;
494                         end
495                         if (!cp_ack) begin
496                                 /* XXX undefined instruction trap */
497                                 $display("WARNING: Possible CDP undefined instruction");
498                         end
499                 end
500                 `DECODE_MRCMCR: if(!inbubble) begin
501                         cp_req = 1;
502                         cp_rnw = insn[20] /* L */;
503                         if (insn[20] == 0 /* store to coprocessor */)
504                                 cp_write = op0;
505                         else begin
506                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
507                                         next_write_reg = 1'b1;
508                                         next_write_num = insn[15:12];
509                                         next_write_data = cp_read;
510                                 end else begin
511                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
512                                         next_outcpsrup = 1;
513                                 end
514                         end
515                         if (cp_busy) begin
516                                 outstall = 1;
517                                 next_outbubble = 1;
518                         end
519                         if (!cp_ack) begin
520                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
521                         end
522                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
523                 end
524                 default: begin end
525                 endcase
526                 
527                 if ((flush || delayedflush) && !outstall)
528                         next_outbubble = 1'b1;
529         end
530 endmodule
This page took 0.112278 seconds and 4 git commands to generate.