[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] odata;

	// synthesis attribute ram_style of rom is block
	reg [7:0] rom [1023:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		odata <= rom[address[10:0]];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] addrlatch = 0;
	reg romno = 0, romnotmp = 0;
	reg [7:0] brom0 [255:0];
	reg [7:0] brom1 [255:0];
	
	initial $readmemh("fpgaboot.hex", brom0);
	initial $readmemh("gbboot.hex", brom1);

	wire decode = address[15:8] == 0;
	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		addrlatch <= address[7:0];
		if (wr && decode) romnotmp <= data[0];
		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg rdlatch = 0;
	reg [7:0] odata;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	
	reg rdlatch = 0, wrlatch = 0;
	reg [15:0] addrlatch = 0;
	reg [7:0] datalatch = 0;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	reg [22:0] progaddr;
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = 0;	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
	
	assign cr_nOE = decode ? ~rdlatch : 1;
	assign cr_nWE = decode ? ~wrlatch : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
			(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
			(addrlatch == ADDR_PROGDATA) ? progaddr :
			23'b0;
	
	reg [7:0] regbuf;
	
	always @(posedge clk) begin
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		ADDR_PROGDATA:	if (rd || wr) begin
					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
					{progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
				end
		endcase
		rdlatch <= rd;
		wrlatch <= wr;
		addrlatch <= address;
		datalatch <= data;
	end
	
	assign data = (rdlatch && decode) ?
				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	input serin,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire serin = 1;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	ROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]),
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWE(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));
	
	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio),
		.serialrx(serin)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule
Commit	Line	Data
a85b19a7 JW	1
	2	`timescale 1ns / 1ps
	3	module ROM(
	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
a8f4468d	9	reg rdlatch = 0;
2854e399 JW	10	reg [7:0] odata;
2854e399 JW	11
91c74a3f	12	// synthesis attribute ram_style of rom is block
fe3dc890	13	reg [7:0] rom [1023:0];
a85b19a7 JW	14	initial $readmemh("rom.hex", rom);
	15
	16	wire decode = address[15:13] == 0;
a8f4468d JW	17	always @(posedge clk) begin
a8f4468d JW	18	rdlatch <= rd && decode;
2854e399	19	odata <= rom[address[10:0]];
a8f4468d JW	20	end
a8f4468d JW	21	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 JW	22	endmodule
a85b19a7 JW	23
91c74a3f JW	24	module BootstrapROM(
	25	input [15:0] address,
	26	inout [7:0] data,
	27	input clk,
	28	input wr, rd);
	29
a8f4468d	30	reg rdlatch = 0;
e29171aa	31	reg [7:0] addrlatch = 0;
49c326da JW	32	reg romno = 0, romnotmp = 0;
	33	reg [7:0] brom0 [255:0];
	34	reg [7:0] brom1 [255:0];
	35
	36	initial $readmemh("fpgaboot.hex", brom0);
	37	initial $readmemh("gbboot.hex", brom1);
91c74a3f JW	38
91c74a3f JW	39	wire decode = address[15:8] == 0;
49c326da	40	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa	41	always @(posedge clk) begin
a8f4468d	42	rdlatch <= rd && decode;
e29171aa	43	addrlatch <= address[7:0];
49c326da JW	44	if (wr && decode) romnotmp <= data[0];
49c326da JW	45	if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa	46	end
a8f4468d	47	assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f JW	48	endmodule
	49
	50	module MiniRAM(
6bd4619b JW	51	input [15:0] address,
	52	inout [7:0] data,
	53	input clk,
	54	input wr, rd);
	55
	56	reg [7:0] ram [127:0];
	57
	58	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d	59	reg rdlatch = 0;
6bd4619b	60	reg [7:0] odata;
a8f4468d	61	assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b	62
68ce013e	63	always @(posedge clk)
6bd4619b	64	begin
a8f4468d JW	65	rdlatch <= rd && decode;
	66	if (decode) // This has to go this way. The only way XST knows how to do
	67	begin // block ram is chip select, write enable, and always
6bd4619b JW	68	if (wr) // reading. "else if rd" does not cut it ...
	69	ram[address[6:0]] <= data;
	70	odata <= ram[address[6:0]];
	71	end
	72	end
c279b666	73	endmodule
6bd4619b	74
74610a87 JW	75	module CellularRAM(
	76	input clk,
	77	input [15:0] address,
	78	inout [7:0] data,
	79	input wr, rd,
	80	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	81	output wire [22:0] cr_A,
	82	inout [15:0] cr_DQ);
	83
	84	parameter ADDR_PROGADDRH = 16'hFF60;
	85	parameter ADDR_PROGADDRM = 16'hFF61;
	86	parameter ADDR_PROGADDRL = 16'hFF62;
	87	parameter ADDR_PROGDATA = 16'hFF63;
	88
a8f4468d JW	89	reg rdlatch = 0, wrlatch = 0;
	90	reg [15:0] addrlatch = 0;
	91	reg [7:0] datalatch = 0;
	92
74610a87 JW	93	reg [7:0] progaddrh, progaddrm, progaddrl;
74610a87 JW	94
1eefdc8e JW	95	reg [22:0] progaddr;
1eefdc8e JW	96
74610a87 JW	97	assign cr_nADV = 0; /* Addresses are always valid! :D */
	98	assign cr_nCE = 0; /* The chip is enabled */
	99	assign cr_nLB = 0; /* Lower byte is enabled */
	100	assign cr_nUB = 0; /* Upper byte is enabled */
	101	assign cr_CRE = 0; /* Data writes, not config */
	102	assign cr_CLK = 0; /* Clock? I think not! */
	103
a8f4468d	104	wire decode = (addrlatch[15:14] == 2'b00) /* extrom / \|\| (addrlatch[15:13] == 3'b101) / extram */ \|\| (addrlatch == ADDR_PROGDATA);
74610a87	105
a8f4468d JW	106	assign cr_nOE = decode ? ~rdlatch : 1;
a8f4468d JW	107	assign cr_nWE = decode ? ~wrlatch : 1;
74610a87	108
a8f4468d JW	109	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	110	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
	111	(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
1eefdc8e	112	(addrlatch == ADDR_PROGDATA) ? progaddr :
74610a87 JW	113	23'b0;
	114
	115	reg [7:0] regbuf;
	116
a8f4468d	117	always @(posedge clk) begin
74610a87 JW	118	case (address)
	119	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	120	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	121	ADDR_PROGADDRL: if (wr) progaddrl <= data;
1eefdc8e JW	122	ADDR_PROGDATA: if (rd \|\| wr) begin
	123	progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
	124	{progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
	125	end
74610a87	126	endcase
a8f4468d JW	127	rdlatch <= rd;
	128	wrlatch <= wr;
	129	addrlatch <= address;
	130	datalatch <= data;
	131	end
74610a87	132
a8f4468d JW	133	assign data = (rdlatch && decode) ?
	134	(addrlatch == ADDR_PROGADDRH) ? progaddrh :
	135	(addrlatch == ADDR_PROGADDRM) ? progaddrm :
	136	(addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87 JW	137	cr_DQ
	138	: 8'bzzzzzzzz;
	139	endmodule
	140
a85b19a7 JW	141	module InternalRAM(
	142	input [15:0] address,
	143	inout [7:0] data,
	144	input clk,
	145	input wr, rd);
	146
fe3dc890	147	// synthesis attribute ram_style of ram is block
616eebe0	148	reg [7:0] ram [8191:0];
a85b19a7	149
74610a87	150	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	151	reg [7:0] odata;
a8f4468d JW	152	reg rdlatch = 0;
a8f4468d JW	153	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	154
68ce013e	155	always @(posedge clk)
a85b19a7	156	begin
a8f4468d	157	rdlatch <= rd && decode;
74610a87 JW	158	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	159	begin // block ram is chip select, write enable, and always
95143d64	160	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	161	ram[address[12:0]] <= data;
616eebe0 JW	162	odata <= ram[address[12:0]];
c87db60a	163	end
a85b19a7 JW	164	end
	165	endmodule
	166
	167	module Switches(
	168	input [15:0] address,
	169	inout [7:0] data,
	170	input clk,
	171	input wr, rd,
	172	input [7:0] switches,
9c834ff2	173	output reg [7:0] ledout = 0);
a85b19a7 JW	174
	175	wire decode = address == 16'hFF51;
	176	reg [7:0] odata;
a8f4468d JW	177	reg rdlatch = 0;
a8f4468d JW	178	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	179
68ce013e	180	always @(posedge clk)
a85b19a7	181	begin
a8f4468d	182	rdlatch <= rd && decode;
a85b19a7 JW	183	if (decode && rd)
	184	odata <= switches;
	185	else if (decode && wr)
	186	ledout <= data;
	187	end
	188	endmodule
	189
e7fb589a JW	190	`ifdef isim
	191	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	192	endmodule
	193	`endif
	194
a85b19a7	195	module CoreTop(
e7fb589a JW	196	`ifdef isim
	197	output reg vgaclk = 0,
	198	output reg clk = 0,
	199	`else
a85b19a7 JW	200	input xtal,
a85b19a7 JW	201	input [7:0] switches,
ff7fd7f2	202	input [3:0] buttons,
a85b19a7 JW	203	output wire [7:0] leds,
a85b19a7 JW	204	output serio,
298e8085	205	input serin,
a85b19a7	206	output wire [3:0] digits,
00573fd5	207	output wire [7:0] seven,
74610a87 JW	208	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	209	output wire [22:0] cr_A,
	210	inout [15:0] cr_DQ,
e7fb589a	211	`endif
00573fd5 JW	212	output wire hs, vs,
00573fd5 JW	213	output wire [2:0] r, g,
09c1936c JW	214	output wire [1:0] b,
09c1936c JW	215	output wire soundl, soundr);
e7fb589a JW	216
	217	`ifdef isim
	218	always #62 clk <= ~clk;
	219	always #100 vgaclk <= ~vgaclk;
	220
	221	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	222
e7fb589a JW	223	wire [7:0] leds;
e7fb589a JW	224	wire serio;
298e8085	225	wire serin = 1;
e7fb589a JW	226	wire [3:0] digits;
	227	wire [7:0] seven;
	228	wire [7:0] switches = 8'b0;
	229	wire [3:0] buttons = 4'b0;
	230	`else
fe3dc890 JW	231	wire xtalb, clk, vgaclk;
	232	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	233	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	234	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	235	`endif
e7fb589a JW	236
91c74a3f JW	237	wire [15:0] addr [1:0];
	238	wire [7:0] data [1:0];
	239	wire wr [1:0], rd [1:0];
f8db6448	240
00573fd5	241	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	242	wire [7:0] jaddr;
6c46357c	243	wire [1:0] state;
179b4347	244
a85b19a7	245	GBZ80Core core(
179b4347	246	.clk(clk),
91c74a3f JW	247	.bus0address(addr[0]),
	248	.bus0data(data[0]),
	249	.bus0wr(wr[0]),
	250	.bus0rd(rd[0]),
	251	.bus1address(addr[1]),
	252	.bus1data(data[1]),
	253	.bus1wr(wr[1]),
	254	.bus1rd(rd[1]),
f8db6448	255	.irq(irq),
6c46357c JW	256	.jaddr(jaddr),
6c46357c JW	257	.state(state));
a85b19a7	258
91c74a3f JW	259	BootstrapROM brom(
	260	.address(addr[1]),
	261	.data(data[1]),
	262	.clk(clk),
	263	.wr(wr[1]),
	264	.rd(rd[1]));
	265
74610a87	266	`ifdef isim
a85b19a7	267	ROM rom(
91c74a3f JW	268	.address(addr[0]),
91c74a3f JW	269	.data(data[0]),
a85b19a7	270	.clk(clk),
91c74a3f JW	271	.wr(wr[0]),
91c74a3f JW	272	.rd(rd[0]));
74610a87 JW	273	`else
	274	CellularRAM cellram(
	275	.address(addr[0]),
	276	.data(data[0]),
	277	.clk(clk),
	278	.wr(wr[0]),
7c1b9e8e	279	.rd(rd[0]),
74610a87 JW	280	.cr_nADV(cr_nADV),
	281	.cr_nCE(cr_nCE),
	282	.cr_nOE(cr_nOE),
7c1b9e8e	283	.cr_nWE(cr_nWE),
74610a87 JW	284	.cr_CRE(cr_CRE),
	285	.cr_nLB(cr_nLB),
	286	.cr_nUB(cr_nUB),
	287	.cr_CLK(cr_CLK),
	288	.cr_A(cr_A),
	289	.cr_DQ(cr_DQ));
	290	`endif
a85b19a7	291
fe3dc890 JW	292	wire lcdhs, lcdvs, lcdclk;
	293	wire [2:0] lcdr, lcdg;
	294	wire [1:0] lcdb;
	295
537e1f83	296	LCDC lcdc(
537e1f83	297	.clk(clk),
91c74a3f JW	298	.addr(addr[0]),
	299	.data(data[0]),
	300	.wr(wr[0]),
	301	.rd(rd[0]),
00573fd5 JW	302	.lcdcirq(lcdcirq),
00573fd5 JW	303	.vblankirq(vblankirq),
fe3dc890 JW	304	.lcdclk(lcdclk),
	305	.lcdhs(lcdhs),
	306	.lcdvs(lcdvs),
	307	.lcdr(lcdr),
	308	.lcdg(lcdg),
	309	.lcdb(lcdb));
	310
	311	Framebuffer fb(
	312	.lcdclk(lcdclk),
	313	.lcdhs(lcdhs),
	314	.lcdvs(lcdvs),
	315	.lcdr(lcdr),
	316	.lcdg(lcdg),
	317	.lcdb(lcdb),
	318	.vgaclk(vgaclk),
00573fd5 JW	319	.vgahs(hs),
	320	.vgavs(vs),
	321	.vgar(r),
	322	.vgag(g),
	323	.vgab(b));
537e1f83	324
a85b19a7	325	AddrMon amon(
eb0f2fe1	326	.clk(clk),
91c74a3f	327	.addr(addr[0]),
eb0f2fe1 JW	328	.digit(digits),
eb0f2fe1 JW	329	.out(seven),
6c46357c JW	330	.freeze(buttons[0]),
6c46357c JW	331	.periods(
179b4347 JW	332	(state == 2'b00) ? 4'b0010 :
	333	(state == 2'b01) ? 4'b0001 :
	334	(state == 2'b10) ? 4'b1000 :
	335	4'b0100) );
a85b19a7 JW	336
a85b19a7 JW	337	Switches sw(
a85b19a7	338	.clk(clk),
91c74a3f JW	339	.address(addr[0]),
	340	.data(data[0]),
	341	.wr(wr[0]),
	342	.rd(rd[0]),
a85b19a7	343	.ledout(leds),
fc443a4f	344	.switches(switches)
a85b19a7 JW	345	);
a85b19a7 JW	346
06ad3a30	347	UART nouart ( /* no u */
91c74a3f JW	348	.clk(clk),
	349	.addr(addr[0]),
	350	.data(data[0]),
	351	.wr(wr[0]),
	352	.rd(rd[0]),
298e8085 JW	353	.serial(serio),
298e8085 JW	354	.serialrx(serin)
eb0f2fe1	355	);
9aa931d1	356
eb0f2fe1	357	InternalRAM ram(
9aa931d1	358	.clk(clk),
91c74a3f JW	359	.address(addr[0]),
	360	.data(data[0]),
	361	.wr(wr[0]),
	362	.rd(rd[0])
eb0f2fe1	363	);
6bd4619b JW	364
6bd4619b JW	365	MiniRAM mram(
6bd4619b	366	.clk(clk),
91c74a3f JW	367	.address(addr[1]),
	368	.data(data[1]),
	369	.wr(wr[1]),
	370	.rd(rd[1])
6bd4619b	371	);
06ad3a30	372
06ad3a30 JW	373	Timer tmr(
06ad3a30 JW	374	.clk(clk),
91c74a3f JW	375	.addr(addr[0]),
	376	.data(data[0]),
	377	.wr(wr[0]),
	378	.rd(rd[0]),
eb0f2fe1 JW	379	.irq(tmrirq)
eb0f2fe1 JW	380	);
06ad3a30 JW	381
	382	Interrupt intr(
	383	.clk(clk),
91c74a3f JW	384	.addr(addr[0]),
	385	.data(data[0]),
	386	.wr(wr[0]),
	387	.rd(rd[0]),
00573fd5	388	.vblank(vblankirq),
537e1f83	389	.lcdc(lcdcirq),
06ad3a30	390	.tovf(tmrirq),
e7fb589a JW	391	.serial(1'b0),
e7fb589a JW	392	.buttons(1'b0),
06ad3a30 JW	393	.master(irq),
06ad3a30 JW	394	.jaddr(jaddr));
09c1936c JW	395
	396	Soundcore sound(
	397	.core_clk(clk),
91c74a3f JW	398	.addr(addr[0]),
	399	.data(data[0]),
	400	.rd(rd[0]),
	401	.wr(wr[0]),
09c1936c JW	402	.snd_data_l(soundl),
09c1936c JW	403	.snd_data_r(soundr));
a85b19a7	404	endmodule