Add chip enable correctness for CellularRAM.
[firearm.git] / system.v
CommitLineData
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1`define BUS_ICACHE 1
2`define BUS_DCACHE 0
ee406839 3
a4f724e6 4module System(input clk, input rst
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5`ifdef verilator
6`else
7 , output wire [8:0] sys_odata,
8 input [8:0] sys_idata,
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9 output wire sys_tookdata,
10
11 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
12 inout wire [15:0] cr_DQ,
13 output wire [22:0] cr_A,
14 output wire st_nCE
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15`endif
16 );
17
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18 wire [7:0] bus_req;
19 wire [7:0] bus_ack;
20 wire [31:0] bus_addr;
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21 wire [31:0] bus_rdata;
22 wire [31:0] bus_wdata;
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23 wire bus_rd, bus_wr;
24 wire bus_ready;
45fa96c0 25
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26 wire bus_req_icache;
27 wire bus_req_dcache;
e3a9107a 28 assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839 29 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381 30 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0 31
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32 wire [31:0] bus_addr_icache;
33 wire [31:0] bus_wdata_icache;
34 wire bus_rd_icache;
35 wire bus_wr_icache;
36
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37 wire [31:0] bus_addr_dcache;
38 wire [31:0] bus_wdata_dcache;
39 wire bus_rd_dcache;
40 wire bus_wr_dcache;
41
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42 wire [31:0] bus_rdata_blockram, bus_rdata_cellularram;
43 wire bus_ready_blockram, bus_ready_cellularram;
a0bb35e7 44
03f45381 45 assign bus_addr = bus_addr_icache | bus_addr_dcache;
1e7ff543 46 assign bus_rdata = bus_rdata_blockram | bus_rdata_cellularram;
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47 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
48 assign bus_rd = bus_rd_icache | bus_rd_dcache;
49 assign bus_wr = bus_wr_icache | bus_wr_dcache;
1e7ff543 50 assign bus_ready = bus_ready_blockram | bus_ready_cellularram;
149bcd1a 51
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52 wire [31:0] icache_rd_addr;
53 wire icache_rd_req;
54 wire icache_rd_wait;
55 wire [31:0] icache_rd_data;
09e28f01 56
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57 wire [31:0] dcache_addr;
58 wire dcache_rd_req, dcache_wr_req;
59 wire dcache_rw_wait;
60 wire [31:0] dcache_wr_data, dcache_rd_data;
61
ab7ee9fc 62 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610 63 wire decode_out_carry;
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64
65 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
66 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
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67 wire regfile_write;
68 wire [3:0] regfile_write_reg;
69 wire [31:0] regfile_write_data;
c65110a8 70
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71 wire execute_out_write_reg;
72 wire [3:0] execute_out_write_num;
73 wire [31:0] execute_out_write_data;
c65110a8 74 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1 75 wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897 76 wire execute_out_cpsrup;
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77
78 wire jmp_out_execute, jmp_out_writeback;
79 wire [31:0] jmppc_out_execute, jmppc_out_writeback;
80 wire jmp = jmp_out_execute | jmp_out_writeback;
81 wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
5ca27949 82
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83 wire memory_out_write_reg;
84 wire [3:0] memory_out_write_num;
85 wire [31:0] memory_out_write_data;
ab7ee9fc 86 wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897 87 wire memory_out_cpsrup;
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88
89 wire [31:0] writeback_out_cpsr, writeback_out_spsr;
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90
91 wire cp_ack_terminal;
92 wire cp_busy_terminal;
93 wire [31:0] cp_read_terminal;
c65110a8 94
43e4332c 95 wire cp_req;
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96 wire [31:0] cp_insn;
97 wire cp_ack = cp_ack_terminal;
98 wire cp_busy = cp_busy_terminal;
43e4332c 99 wire cp_rnw;
1d97a095 100 wire [31:0] cp_read = cp_read_terminal;
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101 wire [31:0] cp_write;
102
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103 wire stall_cause_issue;
104 wire stall_cause_execute;
105 wire stall_cause_memory;
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106 wire bubble_out_fetch;
107 wire bubble_out_issue;
2393422a 108 wire bubble_out_execute;
c65110a8 109 wire bubble_out_memory;
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110 wire [31:0] insn_out_fetch;
111 wire [31:0] insn_out_issue;
2393422a 112 wire [31:0] insn_out_execute;
c65110a8 113 wire [31:0] insn_out_memory;
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114 wire [31:0] pc_out_fetch;
115 wire [31:0] pc_out_issue;
2393422a 116 wire [31:0] pc_out_execute;
c65110a8 117 wire [31:0] pc_out_memory;
2bf779cf 118
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119 wire Nrst = ~rst;
120
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121 /*AUTOWIRE*/
122 // Beginning of automatic wires (for undeclared instantiated-module outputs)
a7297aa5 123 wire bubble_1a; // From fetch of Fetch.v
8c1ba494 124 wire bubble_2a; // From issue of Issue.v
b0e4ff00 125 wire bubble_3a; // From execute of Execute.v
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126 wire carry_2a; // From decode of Decode.v
127 wire [31:0] cpsr_2a; // From decode of Decode.v
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128 wire [31:0] cpsr_3a; // From execute of Execute.v
129 wire cpsrup_3a; // From execute of Execute.v
ed1fdafe 130 wire [31:0] dc__addr_3a; // From memory of Memory.v
b0e4ff00 131 wire [2:0] dc__data_size_3a; // From memory of Memory.v
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132 wire [31:0] dc__rd_data_3a; // From dcache of DCache.v
133 wire dc__rd_req_3a; // From memory of Memory.v
134 wire dc__rw_wait_3a; // From dcache of DCache.v
135 wire [31:0] dc__wr_data_3a; // From memory of Memory.v
136 wire dc__wr_req_3a; // From memory of Memory.v
2bf779cf 137 wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
3c947a99 138 wire [31:0] ic__rd_data_1a; // From icache of ICache.v
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139 wire ic__rd_req_0a; // From fetch of Fetch.v
140 wire ic__rd_wait_0a; // From icache of ICache.v
a7297aa5 141 wire [31:0] insn_1a; // From fetch of Fetch.v
8c1ba494 142 wire [31:0] insn_2a; // From issue of Issue.v
b0e4ff00 143 wire [31:0] insn_3a; // From execute of Execute.v
8c1ba494 144 wire [31:0] op0_2a; // From decode of Decode.v
b0e4ff00 145 wire [31:0] op0_3a; // From execute of Execute.v
8c1ba494 146 wire [31:0] op1_2a; // From decode of Decode.v
b0e4ff00 147 wire [31:0] op1_3a; // From execute of Execute.v
8c1ba494 148 wire [31:0] op2_2a; // From decode of Decode.v
b0e4ff00 149 wire [31:0] op2_3a; // From execute of Execute.v
a7297aa5 150 wire [31:0] pc_1a; // From fetch of Fetch.v
8c1ba494 151 wire [31:0] pc_2a; // From issue of Issue.v
b0e4ff00 152 wire [31:0] pc_3a; // From execute of Execute.v
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153 wire [31:0] rf__rdata_0_1a; // From regfile of RegFile.v
154 wire [31:0] rf__rdata_1_1a; // From regfile of RegFile.v
155 wire [31:0] rf__rdata_2_1a; // From regfile of RegFile.v
b0e4ff00 156 wire [31:0] rf__rdata_3_3a; // From regfile of RegFile.v
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157 wire [3:0] rf__read_0_1a; // From decode of Decode.v
158 wire [3:0] rf__read_1_1a; // From decode of Decode.v
159 wire [3:0] rf__read_2_1a; // From decode of Decode.v
b0e4ff00 160 wire [3:0] rf__read_3_3a; // From memory of Memory.v
8c1ba494 161 wire [31:0] spsr_2a; // From decode of Decode.v
b0e4ff00 162 wire [31:0] spsr_3a; // From execute of Execute.v
ae457ae9 163 wire stall_0a; // From issue of Issue.v
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164 wire [31:0] write_data_3a; // From execute of Execute.v
165 wire [3:0] write_num_3a; // From execute of Execute.v
166 wire write_reg_3a; // From execute of Execute.v
2bf779cf 167 // End of automatics
149bcd1a 168
7947b9c7 169 wire execute_out_backflush;
ab7ee9fc 170 wire writeback_out_backflush;
c2b9d4b7 171
ee406839 172 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7 173
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174 /* XXX reset? */
175 /* ICache AUTO_TEMPLATE (
a0bb35e7 176 .clk(clk),
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177 .bus_req(bus_req_icache),
178 .bus_ack(bus_ack_icache),
179 .bus_addr(bus_addr_icache),
180 .bus_rdata(bus_rdata),
181 .bus_wdata(bus_wdata_icache),
182 .bus_rd(bus_rd_icache),
183 .bus_wr(bus_wr_icache),
184 .bus_ready(bus_ready),
185 ); */
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186 ICache icache(
187 /*AUTOINST*/
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188 // Outputs
189 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 190 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
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191 .bus_req (bus_req_icache), // Templated
192 .bus_addr (bus_addr_icache), // Templated
193 .bus_wdata (bus_wdata_icache), // Templated
194 .bus_rd (bus_rd_icache), // Templated
195 .bus_wr (bus_wr_icache), // Templated
196 // Inputs
197 .clk (clk), // Templated
198 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
199 .ic__rd_req_0a (ic__rd_req_0a),
200 .bus_ack (bus_ack_icache), // Templated
201 .bus_rdata (bus_rdata), // Templated
202 .bus_ready (bus_ready)); // Templated
45fa96c0 203
ed1fdafe 204 /* DCache AUTO_TEMPLATE (
03f45381 205 .clk(clk),
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206 .bus_req(bus_req_dcache),
207 .bus_ack(bus_ack_dcache),
208 .bus_addr(bus_addr_dcache),
209 .bus_rdata(bus_rdata),
210 .bus_wdata(bus_wdata_dcache),
211 .bus_rd(bus_rd_dcache),
212 .bus_wr(bus_wr_dcache),
213 .bus_ready(bus_ready),
214 );
215 */
216 DCache dcache(
217 /*AUTOINST*/
218 // Outputs
219 .dc__rw_wait_3a (dc__rw_wait_3a),
220 .dc__rd_data_3a (dc__rd_data_3a[31:0]),
221 .bus_req (bus_req_dcache), // Templated
222 .bus_addr (bus_addr_dcache), // Templated
223 .bus_wdata (bus_wdata_dcache), // Templated
224 .bus_rd (bus_rd_dcache), // Templated
225 .bus_wr (bus_wr_dcache), // Templated
226 // Inputs
227 .clk (clk), // Templated
228 .dc__addr_3a (dc__addr_3a[31:0]),
229 .dc__rd_req_3a (dc__rd_req_3a),
230 .dc__wr_req_3a (dc__wr_req_3a),
231 .dc__wr_data_3a (dc__wr_data_3a[31:0]),
232 .bus_ack (bus_ack_dcache), // Templated
233 .bus_rdata (bus_rdata), // Templated
234 .bus_ready (bus_ready)); // Templated
03f45381 235
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236`ifdef verilator
237 BigBlockRAM
238`else
239 BlockRAM
240`endif
241 blockram(
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242 .clk(clk),
243 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
244 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
245 .bus_ready(bus_ready_blockram));
246
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247`ifdef verilator
248 assign bus_rdata_cellularram = 32'h00000000;
249 assign bus_ready_cellularram = 0;
250`else
251 /* CellularRAM AUTO_TEMPLATE (
252 .bus_rdata(bus_rdata_cellularram),
253 .bus_ready(bus_ready_cellularram),
254 );
255 */
256 CellularRAM cellularram(
257 /*AUTOINST*/
258 // Outputs
259 .bus_rdata (bus_rdata_cellularram), // Templated
260 .bus_ready (bus_ready_cellularram), // Templated
261 .cr_nADV (cr_nADV),
262 .cr_nCE (cr_nCE),
263 .cr_nOE (cr_nOE),
264 .cr_nWE (cr_nWE),
265 .cr_CRE (cr_CRE),
266 .cr_nLB (cr_nLB),
267 .cr_nUB (cr_nUB),
268 .cr_CLK (cr_CLK),
269 .cr_A (cr_A[22:0]),
270 .st_nCE (st_nCE),
271 // Inouts
272 .cr_DQ (cr_DQ[15:0]),
273 // Inputs
274 .clk (clk),
275 .bus_addr (bus_addr[31:0]),
276 .bus_wdata (bus_wdata[31:0]),
277 .bus_rd (bus_rd),
278 .bus_wr (bus_wr));
279`endif
280
2bf779cf 281 /* Fetch AUTO_TEMPLATE (
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282 .jmp_0a(jmp),
283 .jmppc_0a(jmppc),
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284 );
285 */
286 Fetch fetch(
287 /*AUTOINST*/
288 // Outputs
289 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
290 .ic__rd_req_0a (ic__rd_req_0a),
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291 .bubble_1a (bubble_1a),
292 .insn_1a (insn_1a[31:0]),
293 .pc_1a (pc_1a[31:0]),
2bf779cf 294 // Inputs
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295 .clk (clk),
296 .Nrst (Nrst),
2bf779cf 297 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 298 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
8c1ba494 299 .stall_0a (stall_0a),
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300 .jmp_0a (jmp), // Templated
301 .jmppc_0a (jmppc)); // Templated
09e28f01 302
a7297aa5 303 /* Issue AUTO_TEMPLATE (
ae457ae9 304 .stall_1a(stall_cause_execute),
8c1ba494 305 .flush_1a(execute_out_backflush | writeback_out_backflush),
ae457ae9 306 .cpsr_1a(writeback_out_cpsr),
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307 );
308 */
09e28f01 309 Issue issue(
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310 /*AUTOINST*/
311 // Outputs
ae457ae9 312 .stall_0a (stall_0a),
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313 .bubble_2a (bubble_2a),
314 .pc_2a (pc_2a[31:0]),
315 .insn_2a (insn_2a[31:0]),
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316 // Inputs
317 .clk (clk),
318 .Nrst (Nrst),
ae457ae9 319 .stall_1a (stall_cause_execute), // Templated
8c1ba494 320 .flush_1a (execute_out_backflush | writeback_out_backflush), // Templated
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321 .bubble_1a (bubble_1a),
322 .insn_1a (insn_1a[31:0]),
323 .pc_1a (pc_1a[31:0]),
ae457ae9 324 .cpsr_1a (writeback_out_cpsr)); // Templated
90ff449a 325
a7297aa5 326 /* RegFile AUTO_TEMPLATE (
ab7ee9fc 327 .spsr(regfile_spsr),
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328 .write(regfile_write),
329 .write_reg(regfile_write_reg),
330 .write_data(regfile_write_data),
331 );
332 */
333 wire [3:0] rf__read_3_4a;
334 RegFile regfile(
335 /*AUTOINST*/
336 // Outputs
337 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
338 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
339 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
b0e4ff00 340 .rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
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341 .spsr (regfile_spsr), // Templated
342 // Inputs
343 .clk (clk),
344 .Nrst (Nrst),
345 .rf__read_0_1a (rf__read_0_1a[3:0]),
346 .rf__read_1_1a (rf__read_1_1a[3:0]),
347 .rf__read_2_1a (rf__read_2_1a[3:0]),
b0e4ff00 348 .rf__read_3_3a (rf__read_3_3a[3:0]),
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349 .write (regfile_write), // Templated
350 .write_reg (regfile_write_reg), // Templated
351 .write_data (regfile_write_data)); // Templated
5ca27949 352
a7297aa5 353 /* Decode AUTO_TEMPLATE (
e74c7936 354 .stall(stall_cause_execute),
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355 .cpsr_1a(writeback_out_cpsr),
356 .spsr_1a(writeback_out_spsr),
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357 );
358 */
359 Decode decode(
360 /*AUTOINST*/
361 // Outputs
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362 .op0_2a (op0_2a[31:0]),
363 .op1_2a (op1_2a[31:0]),
364 .op2_2a (op2_2a[31:0]),
365 .carry_2a (carry_2a),
366 .cpsr_2a (cpsr_2a[31:0]),
367 .spsr_2a (spsr_2a[31:0]),
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368 .rf__read_0_1a (rf__read_0_1a[3:0]),
369 .rf__read_1_1a (rf__read_1_1a[3:0]),
370 .rf__read_2_1a (rf__read_2_1a[3:0]),
371 // Inputs
372 .clk (clk),
373 .stall (stall_cause_execute), // Templated
374 .insn_1a (insn_1a[31:0]),
375 .pc_1a (pc_1a[31:0]),
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376 .cpsr_1a (writeback_out_cpsr), // Templated
377 .spsr_1a (writeback_out_spsr), // Templated
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378 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
379 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
380 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]));
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381
382 /* Execute AUTO_TEMPLATE (
383 .stall_2a(stall_cause_memory),
131123bc 384 .flush_2a(writeback_out_backflush),
8c1ba494 385 .outstall_2a(stall_cause_execute),
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386 .jmp_2a(jmp_out_execute),
387 .jmppc_2a(jmppc_out_execute),
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388 );
389 */
bc572c5f 390 Execute execute(
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391 /*AUTOINST*/
392 // Outputs
393 .outstall_2a (stall_cause_execute), // Templated
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394 .bubble_3a (bubble_3a),
395 .cpsr_3a (cpsr_3a[31:0]),
396 .spsr_3a (spsr_3a[31:0]),
397 .cpsrup_3a (cpsrup_3a),
398 .write_reg_3a (write_reg_3a),
399 .write_num_3a (write_num_3a[3:0]),
400 .write_data_3a (write_data_3a[31:0]),
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401 .jmppc_2a (jmppc_out_execute), // Templated
402 .jmp_2a (jmp_out_execute), // Templated
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403 .pc_3a (pc_3a[31:0]),
404 .insn_3a (insn_3a[31:0]),
405 .op0_3a (op0_3a[31:0]),
406 .op1_3a (op1_3a[31:0]),
407 .op2_3a (op2_3a[31:0]),
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408 // Inputs
409 .clk (clk),
410 .Nrst (Nrst),
411 .stall_2a (stall_cause_memory), // Templated
131123bc 412 .flush_2a (writeback_out_backflush), // Templated
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413 .bubble_2a (bubble_2a),
414 .pc_2a (pc_2a[31:0]),
415 .insn_2a (insn_2a[31:0]),
416 .cpsr_2a (cpsr_2a[31:0]),
417 .spsr_2a (spsr_2a[31:0]),
418 .op0_2a (op0_2a[31:0]),
419 .op1_2a (op1_2a[31:0]),
420 .op2_2a (op2_2a[31:0]),
421 .carry_2a (carry_2a));
7947b9c7 422 assign execute_out_backflush = jmp;
c65110a8 423
aa5e9191 424 assign cp_insn = insn_3a;
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425 /* stall? */
426 /* Memory AUTO_TEMPLATE (
427 .flush(writeback_out_backflush),
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428 .outstall(stall_cause_memory),
429 .outbubble(bubble_out_memory),
430 .outpc(pc_out_memory),
431 .outinsn(insn_out_memory),
432 .out_write_reg(memory_out_write_reg),
433 .out_write_num(memory_out_write_num),
43e4332c 434 .out_write_data(memory_out_write_data),
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435 .cp_req(cp_req),
436 .cp_ack(cp_ack),
437 .cp_busy(cp_busy),
438 .cp_rnw(cp_rnw),
439 .cp_read(cp_read),
440 .cp_write(cp_write),
441 .outcpsr(memory_out_cpsr),
442 .outspsr(memory_out_spsr),
443 .outcpsrup(memory_out_cpsrup),
444 );
445 */
446 Memory memory(
447 /*AUTOINST*/
448 // Outputs
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449 .dc__addr_3a (dc__addr_3a[31:0]),
450 .dc__rd_req_3a (dc__rd_req_3a),
451 .dc__wr_req_3a (dc__wr_req_3a),
452 .dc__wr_data_3a (dc__wr_data_3a[31:0]),
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453 .dc__data_size_3a (dc__data_size_3a[2:0]),
454 .rf__read_3_3a (rf__read_3_3a[3:0]),
455 .cp_req (cp_req), // Templated
456 .cp_rnw (cp_rnw), // Templated
457 .cp_write (cp_write), // Templated
458 .outstall (stall_cause_memory), // Templated
459 .outbubble (bubble_out_memory), // Templated
460 .outpc (pc_out_memory), // Templated
461 .outinsn (insn_out_memory), // Templated
462 .out_write_reg (memory_out_write_reg), // Templated
463 .out_write_num (memory_out_write_num), // Templated
464 .out_write_data (memory_out_write_data), // Templated
465 .outspsr (memory_out_spsr), // Templated
466 .outcpsr (memory_out_cpsr), // Templated
467 .outcpsrup (memory_out_cpsrup), // Templated
468 // Inputs
469 .clk (clk),
470 .Nrst (Nrst),
471 .flush (writeback_out_backflush), // Templated
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472 .dc__rw_wait_3a (dc__rw_wait_3a),
473 .dc__rd_data_3a (dc__rd_data_3a[31:0]),
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474 .rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
475 .cp_ack (cp_ack), // Templated
476 .cp_busy (cp_busy), // Templated
477 .cp_read (cp_read), // Templated
478 .bubble_3a (bubble_3a),
479 .pc_3a (pc_3a[31:0]),
480 .insn_3a (insn_3a[31:0]),
481 .op0_3a (op0_3a[31:0]),
482 .op1_3a (op1_3a[31:0]),
483 .op2_3a (op2_3a[31:0]),
484 .spsr_3a (spsr_3a[31:0]),
485 .cpsr_3a (cpsr_3a[31:0]),
486 .cpsrup_3a (cpsrup_3a),
487 .write_reg_3a (write_reg_3a),
488 .write_num_3a (write_num_3a[3:0]),
489 .write_data_3a (write_data_3a[31:0]));
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490
491 Terminal terminal(
492 .clk(clk),
493 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
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494 .cp_read(cp_read_terminal), .cp_write(cp_write)
495`ifdef verilator
496`else
497 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
498`endif
499 );
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500
501 Writeback writeback(
502 .clk(clk),
503 .inbubble(bubble_out_memory),
504 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897 505 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
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506 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
507 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
508 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
509 assign writeback_out_backflush = jmp_out_writeback;
149bcd1a 510
ff39dfc7 511 reg [31:0] clockno = 0;
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512 always @(posedge clk)
513 begin
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514 clockno <= clockno + 1;
515 $display("------------------------------------------------------------------------------");
a7297aa5 516 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
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517 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
518 $display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
aa5e9191 519 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_3a, insn_3a, pc_3a, write_reg_3a, write_data_3a, write_num_3a, jmp_out_execute, jmppc_out_execute);
c65110a8 520 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc 521 $display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a 522 end
ee406839 523endmodule
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