Memory: Input renaming pass.
[firearm.git] / system.v
CommitLineData
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1`define BUS_ICACHE 1
2`define BUS_DCACHE 0
ee406839 3
a4f724e6 4module System(input clk, input rst
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5`ifdef verilator
6`else
7 , output wire [8:0] sys_odata,
8 input [8:0] sys_idata,
9 output wire sys_tookdata
10`endif
11 );
12
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13 wire [7:0] bus_req;
14 wire [7:0] bus_ack;
15 wire [31:0] bus_addr;
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16 wire [31:0] bus_rdata;
17 wire [31:0] bus_wdata;
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18 wire bus_rd, bus_wr;
19 wire bus_ready;
45fa96c0 20
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21 wire bus_req_icache;
22 wire bus_req_dcache;
e3a9107a 23 assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839 24 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381 25 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0 26
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27 wire [31:0] bus_addr_icache;
28 wire [31:0] bus_wdata_icache;
29 wire bus_rd_icache;
30 wire bus_wr_icache;
31
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32 wire [31:0] bus_addr_dcache;
33 wire [31:0] bus_wdata_dcache;
34 wire bus_rd_dcache;
35 wire bus_wr_dcache;
36
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37 wire [31:0] bus_rdata_blockram;
38 wire bus_ready_blockram;
39
03f45381 40 assign bus_addr = bus_addr_icache | bus_addr_dcache;
a0bb35e7 41 assign bus_rdata = bus_rdata_blockram;
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42 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
43 assign bus_rd = bus_rd_icache | bus_rd_dcache;
44 assign bus_wr = bus_wr_icache | bus_wr_dcache;
a0bb35e7 45 assign bus_ready = bus_ready_blockram;
149bcd1a 46
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47 wire [31:0] icache_rd_addr;
48 wire icache_rd_req;
49 wire icache_rd_wait;
50 wire [31:0] icache_rd_data;
09e28f01 51
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52 wire [31:0] dcache_addr;
53 wire dcache_rd_req, dcache_wr_req;
54 wire dcache_rw_wait;
55 wire [31:0] dcache_wr_data, dcache_rd_data;
56
ab7ee9fc 57 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610 58 wire decode_out_carry;
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59
60 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
61 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
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62 wire regfile_write;
63 wire [3:0] regfile_write_reg;
64 wire [31:0] regfile_write_data;
c65110a8 65
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66 wire execute_out_write_reg;
67 wire [3:0] execute_out_write_num;
68 wire [31:0] execute_out_write_data;
c65110a8 69 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1 70 wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897 71 wire execute_out_cpsrup;
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72
73 wire jmp_out_execute, jmp_out_writeback;
74 wire [31:0] jmppc_out_execute, jmppc_out_writeback;
75 wire jmp = jmp_out_execute | jmp_out_writeback;
76 wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
5ca27949 77
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78 wire memory_out_write_reg;
79 wire [3:0] memory_out_write_num;
80 wire [31:0] memory_out_write_data;
ab7ee9fc 81 wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897 82 wire memory_out_cpsrup;
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83
84 wire [31:0] writeback_out_cpsr, writeback_out_spsr;
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85
86 wire cp_ack_terminal;
87 wire cp_busy_terminal;
88 wire [31:0] cp_read_terminal;
c65110a8 89
43e4332c 90 wire cp_req;
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91 wire [31:0] cp_insn;
92 wire cp_ack = cp_ack_terminal;
93 wire cp_busy = cp_busy_terminal;
43e4332c 94 wire cp_rnw;
1d97a095 95 wire [31:0] cp_read = cp_read_terminal;
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96 wire [31:0] cp_write;
97
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98 wire stall_cause_issue;
99 wire stall_cause_execute;
100 wire stall_cause_memory;
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101 wire bubble_out_fetch;
102 wire bubble_out_issue;
2393422a 103 wire bubble_out_execute;
c65110a8 104 wire bubble_out_memory;
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105 wire [31:0] insn_out_fetch;
106 wire [31:0] insn_out_issue;
2393422a 107 wire [31:0] insn_out_execute;
c65110a8 108 wire [31:0] insn_out_memory;
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109 wire [31:0] pc_out_fetch;
110 wire [31:0] pc_out_issue;
2393422a 111 wire [31:0] pc_out_execute;
c65110a8 112 wire [31:0] pc_out_memory;
2bf779cf 113
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114 wire Nrst = ~rst;
115
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116 /*AUTOWIRE*/
117 // Beginning of automatic wires (for undeclared instantiated-module outputs)
a7297aa5 118 wire bubble_1a; // From fetch of Fetch.v
8c1ba494 119 wire bubble_2a; // From issue of Issue.v
b0e4ff00 120 wire bubble_3a; // From execute of Execute.v
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121 wire carry_2a; // From decode of Decode.v
122 wire [31:0] cpsr_2a; // From decode of Decode.v
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123 wire [31:0] cpsr_3a; // From execute of Execute.v
124 wire cpsrup_3a; // From execute of Execute.v
125 wire [2:0] dc__data_size_3a; // From memory of Memory.v
2bf779cf 126 wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
3c947a99 127 wire [31:0] ic__rd_data_1a; // From icache of ICache.v
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128 wire ic__rd_req_0a; // From fetch of Fetch.v
129 wire ic__rd_wait_0a; // From icache of ICache.v
a7297aa5 130 wire [31:0] insn_1a; // From fetch of Fetch.v
8c1ba494 131 wire [31:0] insn_2a; // From issue of Issue.v
b0e4ff00 132 wire [31:0] insn_3a; // From execute of Execute.v
8c1ba494 133 wire [31:0] op0_2a; // From decode of Decode.v
b0e4ff00 134 wire [31:0] op0_3a; // From execute of Execute.v
8c1ba494 135 wire [31:0] op1_2a; // From decode of Decode.v
b0e4ff00 136 wire [31:0] op1_3a; // From execute of Execute.v
8c1ba494 137 wire [31:0] op2_2a; // From decode of Decode.v
b0e4ff00 138 wire [31:0] op2_3a; // From execute of Execute.v
a7297aa5 139 wire [31:0] pc_1a; // From fetch of Fetch.v
8c1ba494 140 wire [31:0] pc_2a; // From issue of Issue.v
b0e4ff00 141 wire [31:0] pc_3a; // From execute of Execute.v
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142 wire [31:0] rf__rdata_0_1a; // From regfile of RegFile.v
143 wire [31:0] rf__rdata_1_1a; // From regfile of RegFile.v
144 wire [31:0] rf__rdata_2_1a; // From regfile of RegFile.v
b0e4ff00 145 wire [31:0] rf__rdata_3_3a; // From regfile of RegFile.v
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146 wire [3:0] rf__read_0_1a; // From decode of Decode.v
147 wire [3:0] rf__read_1_1a; // From decode of Decode.v
148 wire [3:0] rf__read_2_1a; // From decode of Decode.v
b0e4ff00 149 wire [3:0] rf__read_3_3a; // From memory of Memory.v
8c1ba494 150 wire [31:0] spsr_2a; // From decode of Decode.v
b0e4ff00 151 wire [31:0] spsr_3a; // From execute of Execute.v
ae457ae9 152 wire stall_0a; // From issue of Issue.v
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153 wire [31:0] write_data_3a; // From execute of Execute.v
154 wire [3:0] write_num_3a; // From execute of Execute.v
155 wire write_reg_3a; // From execute of Execute.v
2bf779cf 156 // End of automatics
149bcd1a 157
7947b9c7 158 wire execute_out_backflush;
ab7ee9fc 159 wire writeback_out_backflush;
c2b9d4b7 160
ee406839 161 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7 162
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163 /* XXX reset? */
164 /* ICache AUTO_TEMPLATE (
a0bb35e7 165 .clk(clk),
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166 .bus_req(bus_req_icache),
167 .bus_ack(bus_ack_icache),
168 .bus_addr(bus_addr_icache),
169 .bus_rdata(bus_rdata),
170 .bus_wdata(bus_wdata_icache),
171 .bus_rd(bus_rd_icache),
172 .bus_wr(bus_wr_icache),
173 .bus_ready(bus_ready),
174 ); */
175 ICache icache(/*AUTOINST*/
176 // Outputs
177 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 178 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
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179 .bus_req (bus_req_icache), // Templated
180 .bus_addr (bus_addr_icache), // Templated
181 .bus_wdata (bus_wdata_icache), // Templated
182 .bus_rd (bus_rd_icache), // Templated
183 .bus_wr (bus_wr_icache), // Templated
184 // Inputs
185 .clk (clk), // Templated
186 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
187 .ic__rd_req_0a (ic__rd_req_0a),
188 .bus_ack (bus_ack_icache), // Templated
189 .bus_rdata (bus_rdata), // Templated
190 .bus_ready (bus_ready)); // Templated
45fa96c0 191
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192 DCache dcache(
193 .clk(clk),
194 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
195 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
196 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
197 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
198 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
199 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
200
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201`ifdef verilator
202 BigBlockRAM
203`else
204 BlockRAM
205`endif
206 blockram(
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207 .clk(clk),
208 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
209 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
210 .bus_ready(bus_ready_blockram));
211
2bf779cf 212 /* Fetch AUTO_TEMPLATE (
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213 .jmp_0a(jmp),
214 .jmppc_0a(jmppc),
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215 );
216 */
217 Fetch fetch(
218 /*AUTOINST*/
219 // Outputs
220 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
221 .ic__rd_req_0a (ic__rd_req_0a),
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222 .bubble_1a (bubble_1a),
223 .insn_1a (insn_1a[31:0]),
224 .pc_1a (pc_1a[31:0]),
2bf779cf 225 // Inputs
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226 .clk (clk),
227 .Nrst (Nrst),
2bf779cf 228 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 229 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
8c1ba494 230 .stall_0a (stall_0a),
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231 .jmp_0a (jmp), // Templated
232 .jmppc_0a (jmppc)); // Templated
09e28f01 233
a7297aa5 234 /* Issue AUTO_TEMPLATE (
ae457ae9 235 .stall_1a(stall_cause_execute),
8c1ba494 236 .flush_1a(execute_out_backflush | writeback_out_backflush),
ae457ae9 237 .cpsr_1a(writeback_out_cpsr),
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238 );
239 */
09e28f01 240 Issue issue(
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241 /*AUTOINST*/
242 // Outputs
ae457ae9 243 .stall_0a (stall_0a),
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244 .bubble_2a (bubble_2a),
245 .pc_2a (pc_2a[31:0]),
246 .insn_2a (insn_2a[31:0]),
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247 // Inputs
248 .clk (clk),
249 .Nrst (Nrst),
ae457ae9 250 .stall_1a (stall_cause_execute), // Templated
8c1ba494 251 .flush_1a (execute_out_backflush | writeback_out_backflush), // Templated
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252 .bubble_1a (bubble_1a),
253 .insn_1a (insn_1a[31:0]),
254 .pc_1a (pc_1a[31:0]),
ae457ae9 255 .cpsr_1a (writeback_out_cpsr)); // Templated
90ff449a 256
a7297aa5 257 /* RegFile AUTO_TEMPLATE (
ab7ee9fc 258 .spsr(regfile_spsr),
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259 .write(regfile_write),
260 .write_reg(regfile_write_reg),
261 .write_data(regfile_write_data),
262 );
263 */
264 wire [3:0] rf__read_3_4a;
265 RegFile regfile(
266 /*AUTOINST*/
267 // Outputs
268 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
269 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
270 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
b0e4ff00 271 .rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
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272 .spsr (regfile_spsr), // Templated
273 // Inputs
274 .clk (clk),
275 .Nrst (Nrst),
276 .rf__read_0_1a (rf__read_0_1a[3:0]),
277 .rf__read_1_1a (rf__read_1_1a[3:0]),
278 .rf__read_2_1a (rf__read_2_1a[3:0]),
b0e4ff00 279 .rf__read_3_3a (rf__read_3_3a[3:0]),
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280 .write (regfile_write), // Templated
281 .write_reg (regfile_write_reg), // Templated
282 .write_data (regfile_write_data)); // Templated
5ca27949 283
a7297aa5 284 /* Decode AUTO_TEMPLATE (
e74c7936 285 .stall(stall_cause_execute),
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286 .cpsr_1a(writeback_out_cpsr),
287 .spsr_1a(writeback_out_spsr),
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288 );
289 */
290 Decode decode(
291 /*AUTOINST*/
292 // Outputs
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293 .op0_2a (op0_2a[31:0]),
294 .op1_2a (op1_2a[31:0]),
295 .op2_2a (op2_2a[31:0]),
296 .carry_2a (carry_2a),
297 .cpsr_2a (cpsr_2a[31:0]),
298 .spsr_2a (spsr_2a[31:0]),
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299 .rf__read_0_1a (rf__read_0_1a[3:0]),
300 .rf__read_1_1a (rf__read_1_1a[3:0]),
301 .rf__read_2_1a (rf__read_2_1a[3:0]),
302 // Inputs
303 .clk (clk),
304 .stall (stall_cause_execute), // Templated
305 .insn_1a (insn_1a[31:0]),
306 .pc_1a (pc_1a[31:0]),
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307 .cpsr_1a (writeback_out_cpsr), // Templated
308 .spsr_1a (writeback_out_spsr), // Templated
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309 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
310 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
311 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]));
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312
313 /* Execute AUTO_TEMPLATE (
314 .stall_2a(stall_cause_memory),
131123bc 315 .flush_2a(writeback_out_backflush),
8c1ba494 316 .outstall_2a(stall_cause_execute),
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317 .jmp_2a(jmp_out_execute),
318 .jmppc_2a(jmppc_out_execute),
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319 );
320 */
bc572c5f 321 Execute execute(
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322 /*AUTOINST*/
323 // Outputs
324 .outstall_2a (stall_cause_execute), // Templated
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325 .bubble_3a (bubble_3a),
326 .cpsr_3a (cpsr_3a[31:0]),
327 .spsr_3a (spsr_3a[31:0]),
328 .cpsrup_3a (cpsrup_3a),
329 .write_reg_3a (write_reg_3a),
330 .write_num_3a (write_num_3a[3:0]),
331 .write_data_3a (write_data_3a[31:0]),
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332 .jmppc_2a (jmppc_out_execute), // Templated
333 .jmp_2a (jmp_out_execute), // Templated
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334 .pc_3a (pc_3a[31:0]),
335 .insn_3a (insn_3a[31:0]),
336 .op0_3a (op0_3a[31:0]),
337 .op1_3a (op1_3a[31:0]),
338 .op2_3a (op2_3a[31:0]),
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339 // Inputs
340 .clk (clk),
341 .Nrst (Nrst),
342 .stall_2a (stall_cause_memory), // Templated
131123bc 343 .flush_2a (writeback_out_backflush), // Templated
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344 .bubble_2a (bubble_2a),
345 .pc_2a (pc_2a[31:0]),
346 .insn_2a (insn_2a[31:0]),
347 .cpsr_2a (cpsr_2a[31:0]),
348 .spsr_2a (spsr_2a[31:0]),
349 .op0_2a (op0_2a[31:0]),
350 .op1_2a (op1_2a[31:0]),
351 .op2_2a (op2_2a[31:0]),
352 .carry_2a (carry_2a));
7947b9c7 353 assign execute_out_backflush = jmp;
c65110a8 354
1d97a095 355 assign cp_insn = insn_out_execute;
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356 /* stall? */
357 /* Memory AUTO_TEMPLATE (
358 .flush(writeback_out_backflush),
359 .dc__addr_3a(dcache_addr),
360 .dc__rd_req_3a(dcache_rd_req),
361 .dc__wr_req_3a(dcache_wr_req),
362 .dc__rw_wait_3a(dcache_rw_wait),
363 .dc__wr_data_3a(dcache_wr_data),
364 .dc__rd_data_3a(dcache_rd_data),
365 .outstall(stall_cause_memory),
366 .outbubble(bubble_out_memory),
367 .outpc(pc_out_memory),
368 .outinsn(insn_out_memory),
369 .out_write_reg(memory_out_write_reg),
370 .out_write_num(memory_out_write_num),
43e4332c 371 .out_write_data(memory_out_write_data),
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372 .cp_req(cp_req),
373 .cp_ack(cp_ack),
374 .cp_busy(cp_busy),
375 .cp_rnw(cp_rnw),
376 .cp_read(cp_read),
377 .cp_write(cp_write),
378 .outcpsr(memory_out_cpsr),
379 .outspsr(memory_out_spsr),
380 .outcpsrup(memory_out_cpsrup),
381 );
382 */
383 Memory memory(
384 /*AUTOINST*/
385 // Outputs
386 .dc__addr_3a (dcache_addr), // Templated
387 .dc__rd_req_3a (dcache_rd_req), // Templated
388 .dc__wr_req_3a (dcache_wr_req), // Templated
389 .dc__wr_data_3a (dcache_wr_data), // Templated
390 .dc__data_size_3a (dc__data_size_3a[2:0]),
391 .rf__read_3_3a (rf__read_3_3a[3:0]),
392 .cp_req (cp_req), // Templated
393 .cp_rnw (cp_rnw), // Templated
394 .cp_write (cp_write), // Templated
395 .outstall (stall_cause_memory), // Templated
396 .outbubble (bubble_out_memory), // Templated
397 .outpc (pc_out_memory), // Templated
398 .outinsn (insn_out_memory), // Templated
399 .out_write_reg (memory_out_write_reg), // Templated
400 .out_write_num (memory_out_write_num), // Templated
401 .out_write_data (memory_out_write_data), // Templated
402 .outspsr (memory_out_spsr), // Templated
403 .outcpsr (memory_out_cpsr), // Templated
404 .outcpsrup (memory_out_cpsrup), // Templated
405 // Inputs
406 .clk (clk),
407 .Nrst (Nrst),
408 .flush (writeback_out_backflush), // Templated
409 .dc__rw_wait_3a (dcache_rw_wait), // Templated
410 .dc__rd_data_3a (dcache_rd_data), // Templated
411 .rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
412 .cp_ack (cp_ack), // Templated
413 .cp_busy (cp_busy), // Templated
414 .cp_read (cp_read), // Templated
415 .bubble_3a (bubble_3a),
416 .pc_3a (pc_3a[31:0]),
417 .insn_3a (insn_3a[31:0]),
418 .op0_3a (op0_3a[31:0]),
419 .op1_3a (op1_3a[31:0]),
420 .op2_3a (op2_3a[31:0]),
421 .spsr_3a (spsr_3a[31:0]),
422 .cpsr_3a (cpsr_3a[31:0]),
423 .cpsrup_3a (cpsrup_3a),
424 .write_reg_3a (write_reg_3a),
425 .write_num_3a (write_num_3a[3:0]),
426 .write_data_3a (write_data_3a[31:0]));
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427
428 Terminal terminal(
429 .clk(clk),
430 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
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431 .cp_read(cp_read_terminal), .cp_write(cp_write)
432`ifdef verilator
433`else
434 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
435`endif
436 );
ab7ee9fc
JW
437
438 Writeback writeback(
439 .clk(clk),
440 .inbubble(bubble_out_memory),
441 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897 442 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
ab7ee9fc
JW
443 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
444 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
445 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
446 assign writeback_out_backflush = jmp_out_writeback;
149bcd1a 447
ff39dfc7 448 reg [31:0] clockno = 0;
90ff449a
JW
449 always @(posedge clk)
450 begin
ff39dfc7
JW
451 clockno <= clockno + 1;
452 $display("------------------------------------------------------------------------------");
a7297aa5 453 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
8c1ba494
JW
454 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
455 $display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
3550fbf2 456 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8 457 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc 458 $display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a 459 end
ee406839 460endmodule
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