[firearm.git] / system.v

`define BUS_ICACHE 1
`define BUS_DCACHE 0

module System(input clk, input rst
`ifdef verilator
`else
	, output wire [8:0] sys_odata,
	input [8:0] sys_idata,
	output wire sys_tookdata
`endif
	);
	
	wire [7:0] bus_req;
	wire [7:0] bus_ack;
	wire [31:0] bus_addr;
	wire [31:0] bus_rdata;
	wire [31:0] bus_wdata;
	wire bus_rd, bus_wr;
	wire bus_ready;

	wire bus_req_icache;
	wire bus_req_dcache;
	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
	
	wire [31:0] bus_addr_icache;
	wire [31:0] bus_wdata_icache;
	wire bus_rd_icache;
	wire bus_wr_icache;
	
	wire [31:0] bus_addr_dcache;
	wire [31:0] bus_wdata_dcache;
	wire bus_rd_dcache;
	wire bus_wr_dcache;
	
	wire [31:0] bus_rdata_blockram;
	wire bus_ready_blockram;
	
	assign bus_addr = bus_addr_icache | bus_addr_dcache;
	assign bus_rdata = bus_rdata_blockram;
	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
	assign bus_rd = bus_rd_icache | bus_rd_dcache;
	assign bus_wr = bus_wr_icache | bus_wr_dcache;
	assign bus_ready = bus_ready_blockram;

	wire [31:0] icache_rd_addr;
	wire icache_rd_req;
	wire icache_rd_wait;
	wire [31:0] icache_rd_data;
	
	wire [31:0] dcache_addr;
	wire dcache_rd_req, dcache_wr_req;
	wire dcache_rw_wait;
	wire [31:0] dcache_wr_data, dcache_rd_data;
	
	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
	wire decode_out_carry;
	
	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	wire regfile_write;
	wire [3:0] regfile_write_reg;
	wire [31:0] regfile_write_data;
	
	wire execute_out_write_reg;
	wire [3:0] execute_out_write_num;
	wire [31:0] execute_out_write_data;
	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
	wire [31:0] execute_out_cpsr, execute_out_spsr;
	wire execute_out_cpsrup;
	
	wire jmp_out_execute, jmp_out_writeback;
	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	wire jmp = jmp_out_execute | jmp_out_writeback;
	wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
	
	wire memory_out_write_reg;
	wire [3:0] memory_out_write_num;
	wire [31:0] memory_out_write_data;
	wire [31:0] memory_out_cpsr, memory_out_spsr;
	wire memory_out_cpsrup;
	
	wire [31:0] writeback_out_cpsr, writeback_out_spsr;

	wire cp_ack_terminal;
	wire cp_busy_terminal;
	wire [31:0] cp_read_terminal;
	
	wire cp_req;
	wire [31:0] cp_insn;
	wire cp_ack = cp_ack_terminal;
	wire cp_busy = cp_busy_terminal;
	wire cp_rnw;
	wire [31:0] cp_read = cp_read_terminal;
	wire [31:0] cp_write;
	
	wire stall_cause_issue;
	wire stall_cause_execute;
	wire stall_cause_memory;
	wire bubble_out_fetch;
	wire bubble_out_issue;
	wire bubble_out_execute;
	wire bubble_out_memory;
	wire [31:0] insn_out_fetch;
	wire [31:0] insn_out_issue;
	wire [31:0] insn_out_execute;
	wire [31:0] insn_out_memory;
	wire [31:0] pc_out_fetch;
	wire [31:0] pc_out_issue;
	wire [31:0] pc_out_execute;
	wire [31:0] pc_out_memory;
	
	wire Nrst = ~rst;
	
	/*AUTOWIRE*/
	// Beginning of automatic wires (for undeclared instantiated-module outputs)
	wire		bubble_1a;		// From fetch of Fetch.v
	wire		bubble_2a;		// From issue of Issue.v
	wire		bubble_3a;		// From execute of Execute.v
	wire		carry_2a;		// From decode of Decode.v
	wire [31:0]	cpsr_2a;		// From decode of Decode.v
	wire [31:0]	cpsr_3a;		// From execute of Execute.v
	wire		cpsrup_3a;		// From execute of Execute.v
	wire [31:0]	dc__addr_3a;		// From memory of Memory.v
	wire [2:0]	dc__data_size_3a;	// From memory of Memory.v
	wire [31:0]	dc__rd_data_3a;		// From dcache of DCache.v
	wire		dc__rd_req_3a;		// From memory of Memory.v
	wire		dc__rw_wait_3a;		// From dcache of DCache.v
	wire [31:0]	dc__wr_data_3a;		// From memory of Memory.v
	wire		dc__wr_req_3a;		// From memory of Memory.v
	wire [31:0]	ic__rd_addr_0a;		// From fetch of Fetch.v
	wire [31:0]	ic__rd_data_1a;		// From icache of ICache.v
	wire		ic__rd_req_0a;		// From fetch of Fetch.v
	wire		ic__rd_wait_0a;		// From icache of ICache.v
	wire [31:0]	insn_1a;		// From fetch of Fetch.v
	wire [31:0]	insn_2a;		// From issue of Issue.v
	wire [31:0]	insn_3a;		// From execute of Execute.v
	wire [31:0]	op0_2a;			// From decode of Decode.v
	wire [31:0]	op0_3a;			// From execute of Execute.v
	wire [31:0]	op1_2a;			// From decode of Decode.v
	wire [31:0]	op1_3a;			// From execute of Execute.v
	wire [31:0]	op2_2a;			// From decode of Decode.v
	wire [31:0]	op2_3a;			// From execute of Execute.v
	wire [31:0]	pc_1a;			// From fetch of Fetch.v
	wire [31:0]	pc_2a;			// From issue of Issue.v
	wire [31:0]	pc_3a;			// From execute of Execute.v
	wire [31:0]	rf__rdata_0_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_1_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_2_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_3_3a;		// From regfile of RegFile.v
	wire [3:0]	rf__read_0_1a;		// From decode of Decode.v
	wire [3:0]	rf__read_1_1a;		// From decode of Decode.v
	wire [3:0]	rf__read_2_1a;		// From decode of Decode.v
	wire [3:0]	rf__read_3_3a;		// From memory of Memory.v
	wire [31:0]	spsr_2a;		// From decode of Decode.v
	wire [31:0]	spsr_3a;		// From execute of Execute.v
	wire		stall_0a;		// From issue of Issue.v
	wire [31:0]	write_data_3a;		// From execute of Execute.v
	wire [3:0]	write_num_3a;		// From execute of Execute.v
	wire		write_reg_3a;		// From execute of Execute.v
	// End of automatics

	wire execute_out_backflush;
	wire writeback_out_backflush;

	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));

	/* XXX reset? */
	/* ICache AUTO_TEMPLATE (
		.clk(clk),
		.bus_req(bus_req_icache),
		.bus_ack(bus_ack_icache),
		.bus_addr(bus_addr_icache),
		.bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_icache),
		.bus_rd(bus_rd_icache),
		.bus_wr(bus_wr_icache),
		.bus_ready(bus_ready),
		); */
	ICache icache(
		/*AUTOINST*/
		      // Outputs
		      .ic__rd_wait_0a	(ic__rd_wait_0a),
		      .ic__rd_data_1a	(ic__rd_data_1a[31:0]),
		      .bus_req		(bus_req_icache),	 // Templated
		      .bus_addr		(bus_addr_icache),	 // Templated
		      .bus_wdata	(bus_wdata_icache),	 // Templated
		      .bus_rd		(bus_rd_icache),	 // Templated
		      .bus_wr		(bus_wr_icache),	 // Templated
		      // Inputs
		      .clk		(clk),			 // Templated
		      .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		      .ic__rd_req_0a	(ic__rd_req_0a),
		      .bus_ack		(bus_ack_icache),	 // Templated
		      .bus_rdata	(bus_rdata),		 // Templated
		      .bus_ready	(bus_ready));		 // Templated
	
	/* DCache AUTO_TEMPLATE (
		.clk(clk),
		.bus_req(bus_req_dcache),
		.bus_ack(bus_ack_dcache),
		.bus_addr(bus_addr_dcache),
		.bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_dcache),
		.bus_rd(bus_rd_dcache),
		.bus_wr(bus_wr_dcache),
		.bus_ready(bus_ready),
		);
		*/
	DCache dcache(
		/*AUTOINST*/
		      // Outputs
		      .dc__rw_wait_3a	(dc__rw_wait_3a),
		      .dc__rd_data_3a	(dc__rd_data_3a[31:0]),
		      .bus_req		(bus_req_dcache),	 // Templated
		      .bus_addr		(bus_addr_dcache),	 // Templated
		      .bus_wdata	(bus_wdata_dcache),	 // Templated
		      .bus_rd		(bus_rd_dcache),	 // Templated
		      .bus_wr		(bus_wr_dcache),	 // Templated
		      // Inputs
		      .clk		(clk),			 // Templated
		      .dc__addr_3a	(dc__addr_3a[31:0]),
		      .dc__rd_req_3a	(dc__rd_req_3a),
		      .dc__wr_req_3a	(dc__wr_req_3a),
		      .dc__wr_data_3a	(dc__wr_data_3a[31:0]),
		      .bus_ack		(bus_ack_dcache),	 // Templated
		      .bus_rdata	(bus_rdata),		 // Templated
		      .bus_ready	(bus_ready));		 // Templated

`ifdef verilator
	BigBlockRAM
`else
	BlockRAM
`endif
	blockram(
		.clk(clk),
		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
		.bus_ready(bus_ready_blockram));

	/* Fetch AUTO_TEMPLATE (
		.jmp_0a(jmp),
		.jmppc_0a(jmppc),
		);
	*/
	Fetch fetch(
		/*AUTOINST*/
		    // Outputs
		    .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		    .ic__rd_req_0a	(ic__rd_req_0a),
		    .bubble_1a		(bubble_1a),
		    .insn_1a		(insn_1a[31:0]),
		    .pc_1a		(pc_1a[31:0]),
		    // Inputs
		    .clk		(clk),
		    .Nrst		(Nrst),
		    .ic__rd_wait_0a	(ic__rd_wait_0a),
		    .ic__rd_data_1a	(ic__rd_data_1a[31:0]),
		    .stall_0a		(stall_0a),
		    .jmp_0a		(jmp),			 // Templated
		    .jmppc_0a		(jmppc));		 // Templated
	
	/* Issue AUTO_TEMPLATE (
		.stall_1a(stall_cause_execute),
		.flush_1a(execute_out_backflush | writeback_out_backflush),
		.cpsr_1a(writeback_out_cpsr),
		);
	*/
	Issue issue(
		/*AUTOINST*/
		    // Outputs
		    .stall_0a		(stall_0a),
		    .bubble_2a		(bubble_2a),
		    .pc_2a		(pc_2a[31:0]),
		    .insn_2a		(insn_2a[31:0]),
		    // Inputs
		    .clk		(clk),
		    .Nrst		(Nrst),
		    .stall_1a		(stall_cause_execute),	 // Templated
		    .flush_1a		(execute_out_backflush | writeback_out_backflush), // Templated
		    .bubble_1a		(bubble_1a),
		    .insn_1a		(insn_1a[31:0]),
		    .pc_1a		(pc_1a[31:0]),
		    .cpsr_1a		(writeback_out_cpsr));	 // Templated
	
	/* RegFile AUTO_TEMPLATE (
		.spsr(regfile_spsr),
		.write(regfile_write),
		.write_reg(regfile_write_reg),
		.write_data(regfile_write_data),
		);
	*/
	wire [3:0] rf__read_3_4a;
	RegFile regfile(
		/*AUTOINST*/
			// Outputs
			.rf__rdata_0_1a	(rf__rdata_0_1a[31:0]),
			.rf__rdata_1_1a	(rf__rdata_1_1a[31:0]),
			.rf__rdata_2_1a	(rf__rdata_2_1a[31:0]),
			.rf__rdata_3_3a	(rf__rdata_3_3a[31:0]),
			.spsr		(regfile_spsr),		 // Templated
			// Inputs
			.clk		(clk),
			.Nrst		(Nrst),
			.rf__read_0_1a	(rf__read_0_1a[3:0]),
			.rf__read_1_1a	(rf__read_1_1a[3:0]),
			.rf__read_2_1a	(rf__read_2_1a[3:0]),
			.rf__read_3_3a	(rf__read_3_3a[3:0]),
			.write		(regfile_write),	 // Templated
			.write_reg	(regfile_write_reg),	 // Templated
			.write_data	(regfile_write_data));	 // Templated
	
	/* Decode AUTO_TEMPLATE (
		.stall(stall_cause_execute),
		.cpsr_1a(writeback_out_cpsr),
		.spsr_1a(writeback_out_spsr),
		);
	*/
	Decode decode(
		/*AUTOINST*/
		      // Outputs
		      .op0_2a		(op0_2a[31:0]),
		      .op1_2a		(op1_2a[31:0]),
		      .op2_2a		(op2_2a[31:0]),
		      .carry_2a		(carry_2a),
		      .cpsr_2a		(cpsr_2a[31:0]),
		      .spsr_2a		(spsr_2a[31:0]),
		      .rf__read_0_1a	(rf__read_0_1a[3:0]),
		      .rf__read_1_1a	(rf__read_1_1a[3:0]),
		      .rf__read_2_1a	(rf__read_2_1a[3:0]),
		      // Inputs
		      .clk		(clk),
		      .stall		(stall_cause_execute),	 // Templated
		      .insn_1a		(insn_1a[31:0]),
		      .pc_1a		(pc_1a[31:0]),
		      .cpsr_1a		(writeback_out_cpsr),	 // Templated
		      .spsr_1a		(writeback_out_spsr),	 // Templated
		      .rf__rdata_0_1a	(rf__rdata_0_1a[31:0]),
		      .rf__rdata_1_1a	(rf__rdata_1_1a[31:0]),
		      .rf__rdata_2_1a	(rf__rdata_2_1a[31:0]));

	/* Execute AUTO_TEMPLATE (
		.stall_2a(stall_cause_memory),
		.flush_2a(writeback_out_backflush),
		.outstall_2a(stall_cause_execute),
		.jmp_2a(jmp_out_execute),
		.jmppc_2a(jmppc_out_execute),
		);
	*/	
	Execute execute(
		/*AUTOINST*/
			// Outputs
			.outstall_2a	(stall_cause_execute),	 // Templated
			.bubble_3a	(bubble_3a),
			.cpsr_3a	(cpsr_3a[31:0]),
			.spsr_3a	(spsr_3a[31:0]),
			.cpsrup_3a	(cpsrup_3a),
			.write_reg_3a	(write_reg_3a),
			.write_num_3a	(write_num_3a[3:0]),
			.write_data_3a	(write_data_3a[31:0]),
			.jmppc_2a	(jmppc_out_execute),	 // Templated
			.jmp_2a		(jmp_out_execute),	 // Templated
			.pc_3a		(pc_3a[31:0]),
			.insn_3a	(insn_3a[31:0]),
			.op0_3a		(op0_3a[31:0]),
			.op1_3a		(op1_3a[31:0]),
			.op2_3a		(op2_3a[31:0]),
			// Inputs
			.clk		(clk),
			.Nrst		(Nrst),
			.stall_2a	(stall_cause_memory),	 // Templated
			.flush_2a	(writeback_out_backflush), // Templated
			.bubble_2a	(bubble_2a),
			.pc_2a		(pc_2a[31:0]),
			.insn_2a	(insn_2a[31:0]),
			.cpsr_2a	(cpsr_2a[31:0]),
			.spsr_2a	(spsr_2a[31:0]),
			.op0_2a		(op0_2a[31:0]),
			.op1_2a		(op1_2a[31:0]),
			.op2_2a		(op2_2a[31:0]),
			.carry_2a	(carry_2a));
	assign execute_out_backflush = jmp;
	
	assign cp_insn = insn_out_execute;
	/* stall? */
	/* Memory AUTO_TEMPLATE (
		.flush(writeback_out_backflush),
		.outstall(stall_cause_memory),
		.outbubble(bubble_out_memory), 
		.outpc(pc_out_memory),
		.outinsn(insn_out_memory),
		.out_write_reg(memory_out_write_reg),
		.out_write_num(memory_out_write_num), 
		.out_write_data(memory_out_write_data),
		.cp_req(cp_req),
		.cp_ack(cp_ack),
		.cp_busy(cp_busy),
		.cp_rnw(cp_rnw),
		.cp_read(cp_read),
		.cp_write(cp_write),
		.outcpsr(memory_out_cpsr),
		.outspsr(memory_out_spsr),
		.outcpsrup(memory_out_cpsrup),
		);
		*/
	Memory memory(
		/*AUTOINST*/
		      // Outputs
		      .dc__addr_3a	(dc__addr_3a[31:0]),
		      .dc__rd_req_3a	(dc__rd_req_3a),
		      .dc__wr_req_3a	(dc__wr_req_3a),
		      .dc__wr_data_3a	(dc__wr_data_3a[31:0]),
		      .dc__data_size_3a	(dc__data_size_3a[2:0]),
		      .rf__read_3_3a	(rf__read_3_3a[3:0]),
		      .cp_req		(cp_req),		 // Templated
		      .cp_rnw		(cp_rnw),		 // Templated
		      .cp_write		(cp_write),		 // Templated
		      .outstall		(stall_cause_memory),	 // Templated
		      .outbubble	(bubble_out_memory),	 // Templated
		      .outpc		(pc_out_memory),	 // Templated
		      .outinsn		(insn_out_memory),	 // Templated
		      .out_write_reg	(memory_out_write_reg),	 // Templated
		      .out_write_num	(memory_out_write_num),	 // Templated
		      .out_write_data	(memory_out_write_data), // Templated
		      .outspsr		(memory_out_spsr),	 // Templated
		      .outcpsr		(memory_out_cpsr),	 // Templated
		      .outcpsrup	(memory_out_cpsrup),	 // Templated
		      // Inputs
		      .clk		(clk),
		      .Nrst		(Nrst),
		      .flush		(writeback_out_backflush), // Templated
		      .dc__rw_wait_3a	(dc__rw_wait_3a),
		      .dc__rd_data_3a	(dc__rd_data_3a[31:0]),
		      .rf__rdata_3_3a	(rf__rdata_3_3a[31:0]),
		      .cp_ack		(cp_ack),		 // Templated
		      .cp_busy		(cp_busy),		 // Templated
		      .cp_read		(cp_read),		 // Templated
		      .bubble_3a	(bubble_3a),
		      .pc_3a		(pc_3a[31:0]),
		      .insn_3a		(insn_3a[31:0]),
		      .op0_3a		(op0_3a[31:0]),
		      .op1_3a		(op1_3a[31:0]),
		      .op2_3a		(op2_3a[31:0]),
		      .spsr_3a		(spsr_3a[31:0]),
		      .cpsr_3a		(cpsr_3a[31:0]),
		      .cpsrup_3a	(cpsrup_3a),
		      .write_reg_3a	(write_reg_3a),
		      .write_num_3a	(write_num_3a[3:0]),
		      .write_data_3a	(write_data_3a[31:0]));
	
	Terminal terminal(	
		.clk(clk),
		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
		.cp_read(cp_read_terminal), .cp_write(cp_write)
`ifdef verilator
`else
		, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
`endif
		);
	
	Writeback writeback(
		.clk(clk),
		.inbubble(bubble_out_memory),
		.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
		.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
		.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
		.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	assign writeback_out_backflush = jmp_out_writeback;

	reg [31:0] clockno = 0;
	always @(posedge clk)
	begin
		clockno <= clockno + 1;
		$display("------------------------------------------------------------------------------");
		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
	end
endmodule
Commit	Line	Data
e3a9107a JW	1	`define BUS_ICACHE 1
e3a9107a JW	2	`define BUS_DCACHE 0
ee406839	3
a4f724e6	4	module System(input clk, input rst
fd003c7a JW	5	`ifdef verilator
	6	`else
	7	, output wire [8:0] sys_odata,
	8	input [8:0] sys_idata,
	9	output wire sys_tookdata
	10	`endif
	11	);
	12
ee406839 JW	13	wire [7:0] bus_req;
	14	wire [7:0] bus_ack;
	15	wire [31:0] bus_addr;
a0bb35e7 JW	16	wire [31:0] bus_rdata;
a0bb35e7 JW	17	wire [31:0] bus_wdata;
ee406839 JW	18	wire bus_rd, bus_wr;
ee406839 JW	19	wire bus_ready;
45fa96c0	20
03f45381 JW	21	wire bus_req_icache;
03f45381 JW	22	wire bus_req_dcache;
e3a9107a	23	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839	24	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381	25	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0	26
ee406839 JW	27	wire [31:0] bus_addr_icache;
	28	wire [31:0] bus_wdata_icache;
	29	wire bus_rd_icache;
	30	wire bus_wr_icache;
	31
03f45381 JW	32	wire [31:0] bus_addr_dcache;
	33	wire [31:0] bus_wdata_dcache;
	34	wire bus_rd_dcache;
	35	wire bus_wr_dcache;
	36
a0bb35e7 JW	37	wire [31:0] bus_rdata_blockram;
	38	wire bus_ready_blockram;
	39
03f45381	40	assign bus_addr = bus_addr_icache \| bus_addr_dcache;
a0bb35e7	41	assign bus_rdata = bus_rdata_blockram;
03f45381 JW	42	assign bus_wdata = bus_wdata_icache \| bus_wdata_dcache;
	43	assign bus_rd = bus_rd_icache \| bus_rd_dcache;
	44	assign bus_wr = bus_wr_icache \| bus_wr_dcache;
a0bb35e7	45	assign bus_ready = bus_ready_blockram;
149bcd1a	46
5d9760a4 JW	47	wire [31:0] icache_rd_addr;
	48	wire icache_rd_req;
	49	wire icache_rd_wait;
	50	wire [31:0] icache_rd_data;
09e28f01	51
03f45381 JW	52	wire [31:0] dcache_addr;
	53	wire dcache_rd_req, dcache_wr_req;
	54	wire dcache_rw_wait;
	55	wire [31:0] dcache_wr_data, dcache_rd_data;
	56
ab7ee9fc	57	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610	58	wire decode_out_carry;
c65110a8 JW	59
	60	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	61	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
ab7ee9fc JW	62	wire regfile_write;
	63	wire [3:0] regfile_write_reg;
	64	wire [31:0] regfile_write_data;
c65110a8	65
bc572c5f JW	66	wire execute_out_write_reg;
	67	wire [3:0] execute_out_write_num;
	68	wire [31:0] execute_out_write_data;
c65110a8	69	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1	70	wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897	71	wire execute_out_cpsrup;
ab7ee9fc JW	72
	73	wire jmp_out_execute, jmp_out_writeback;
	74	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	75	wire jmp = jmp_out_execute \| jmp_out_writeback;
	76	wire [31:0] jmppc = jmppc_out_execute \| jmppc_out_writeback;
5ca27949	77
c65110a8 JW	78	wire memory_out_write_reg;
	79	wire [3:0] memory_out_write_num;
	80	wire [31:0] memory_out_write_data;
ab7ee9fc	81	wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897	82	wire memory_out_cpsrup;
ab7ee9fc JW	83
ab7ee9fc JW	84	wire [31:0] writeback_out_cpsr, writeback_out_spsr;
1d97a095 JW	85
	86	wire cp_ack_terminal;
	87	wire cp_busy_terminal;
	88	wire [31:0] cp_read_terminal;
c65110a8	89
43e4332c	90	wire cp_req;
1d97a095 JW	91	wire [31:0] cp_insn;
	92	wire cp_ack = cp_ack_terminal;
	93	wire cp_busy = cp_busy_terminal;
43e4332c	94	wire cp_rnw;
1d97a095	95	wire [31:0] cp_read = cp_read_terminal;
43e4332c JW	96	wire [31:0] cp_write;
43e4332c JW	97
c65110a8 JW	98	wire stall_cause_issue;
	99	wire stall_cause_execute;
	100	wire stall_cause_memory;
09e28f01 JW	101	wire bubble_out_fetch;
09e28f01 JW	102	wire bubble_out_issue;
2393422a	103	wire bubble_out_execute;
c65110a8	104	wire bubble_out_memory;
09e28f01 JW	105	wire [31:0] insn_out_fetch;
09e28f01 JW	106	wire [31:0] insn_out_issue;
2393422a	107	wire [31:0] insn_out_execute;
c65110a8	108	wire [31:0] insn_out_memory;
09e28f01 JW	109	wire [31:0] pc_out_fetch;
09e28f01 JW	110	wire [31:0] pc_out_issue;
2393422a	111	wire [31:0] pc_out_execute;
c65110a8	112	wire [31:0] pc_out_memory;
2bf779cf	113
a7297aa5 JW	114	wire Nrst = ~rst;
a7297aa5 JW	115
2bf779cf JW	116	/AUTOWIRE/
2bf779cf JW	117	// Beginning of automatic wires (for undeclared instantiated-module outputs)
a7297aa5	118	wire bubble_1a; // From fetch of Fetch.v
8c1ba494	119	wire bubble_2a; // From issue of Issue.v
b0e4ff00	120	wire bubble_3a; // From execute of Execute.v
8c1ba494 JW	121	wire carry_2a; // From decode of Decode.v
8c1ba494 JW	122	wire [31:0] cpsr_2a; // From decode of Decode.v
b0e4ff00 JW	123	wire [31:0] cpsr_3a; // From execute of Execute.v
b0e4ff00 JW	124	wire cpsrup_3a; // From execute of Execute.v
ed1fdafe	125	wire [31:0] dc__addr_3a; // From memory of Memory.v
b0e4ff00	126	wire [2:0] dc__data_size_3a; // From memory of Memory.v
ed1fdafe JW	127	wire [31:0] dc__rd_data_3a; // From dcache of DCache.v
	128	wire dc__rd_req_3a; // From memory of Memory.v
	129	wire dc__rw_wait_3a; // From dcache of DCache.v
	130	wire [31:0] dc__wr_data_3a; // From memory of Memory.v
	131	wire dc__wr_req_3a; // From memory of Memory.v
2bf779cf	132	wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
3c947a99	133	wire [31:0] ic__rd_data_1a; // From icache of ICache.v
2bf779cf JW	134	wire ic__rd_req_0a; // From fetch of Fetch.v
2bf779cf JW	135	wire ic__rd_wait_0a; // From icache of ICache.v
a7297aa5	136	wire [31:0] insn_1a; // From fetch of Fetch.v
8c1ba494	137	wire [31:0] insn_2a; // From issue of Issue.v
b0e4ff00	138	wire [31:0] insn_3a; // From execute of Execute.v
8c1ba494	139	wire [31:0] op0_2a; // From decode of Decode.v
b0e4ff00	140	wire [31:0] op0_3a; // From execute of Execute.v
8c1ba494	141	wire [31:0] op1_2a; // From decode of Decode.v
b0e4ff00	142	wire [31:0] op1_3a; // From execute of Execute.v
8c1ba494	143	wire [31:0] op2_2a; // From decode of Decode.v
b0e4ff00	144	wire [31:0] op2_3a; // From execute of Execute.v
a7297aa5	145	wire [31:0] pc_1a; // From fetch of Fetch.v
8c1ba494	146	wire [31:0] pc_2a; // From issue of Issue.v
b0e4ff00	147	wire [31:0] pc_3a; // From execute of Execute.v
a7297aa5 JW	148	wire [31:0] rf__rdata_0_1a; // From regfile of RegFile.v
	149	wire [31:0] rf__rdata_1_1a; // From regfile of RegFile.v
	150	wire [31:0] rf__rdata_2_1a; // From regfile of RegFile.v
b0e4ff00	151	wire [31:0] rf__rdata_3_3a; // From regfile of RegFile.v
a7297aa5 JW	152	wire [3:0] rf__read_0_1a; // From decode of Decode.v
	153	wire [3:0] rf__read_1_1a; // From decode of Decode.v
	154	wire [3:0] rf__read_2_1a; // From decode of Decode.v
b0e4ff00	155	wire [3:0] rf__read_3_3a; // From memory of Memory.v
8c1ba494	156	wire [31:0] spsr_2a; // From decode of Decode.v
b0e4ff00	157	wire [31:0] spsr_3a; // From execute of Execute.v
ae457ae9	158	wire stall_0a; // From issue of Issue.v
b0e4ff00 JW	159	wire [31:0] write_data_3a; // From execute of Execute.v
	160	wire [3:0] write_num_3a; // From execute of Execute.v
	161	wire write_reg_3a; // From execute of Execute.v
2bf779cf	162	// End of automatics
149bcd1a	163
7947b9c7	164	wire execute_out_backflush;
ab7ee9fc	165	wire writeback_out_backflush;
c2b9d4b7	166
ee406839	167	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7	168
2bf779cf JW	169	/* XXX reset? */
2bf779cf JW	170	/* ICache AUTO_TEMPLATE (
a0bb35e7	171	.clk(clk),
2bf779cf JW	172	.bus_req(bus_req_icache),
	173	.bus_ack(bus_ack_icache),
	174	.bus_addr(bus_addr_icache),
	175	.bus_rdata(bus_rdata),
	176	.bus_wdata(bus_wdata_icache),
	177	.bus_rd(bus_rd_icache),
	178	.bus_wr(bus_wr_icache),
	179	.bus_ready(bus_ready),
	180	); */
ed1fdafe JW	181	ICache icache(
ed1fdafe JW	182	/AUTOINST/
2bf779cf JW	183	// Outputs
2bf779cf JW	184	.ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99	185	.ic__rd_data_1a (ic__rd_data_1a[31:0]),
2bf779cf JW	186	.bus_req (bus_req_icache), // Templated
	187	.bus_addr (bus_addr_icache), // Templated
	188	.bus_wdata (bus_wdata_icache), // Templated
	189	.bus_rd (bus_rd_icache), // Templated
	190	.bus_wr (bus_wr_icache), // Templated
	191	// Inputs
	192	.clk (clk), // Templated
	193	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	194	.ic__rd_req_0a (ic__rd_req_0a),
	195	.bus_ack (bus_ack_icache), // Templated
	196	.bus_rdata (bus_rdata), // Templated
	197	.bus_ready (bus_ready)); // Templated
45fa96c0	198
ed1fdafe	199	/* DCache AUTO_TEMPLATE (
03f45381	200	.clk(clk),
ed1fdafe JW	201	.bus_req(bus_req_dcache),
	202	.bus_ack(bus_ack_dcache),
	203	.bus_addr(bus_addr_dcache),
	204	.bus_rdata(bus_rdata),
	205	.bus_wdata(bus_wdata_dcache),
	206	.bus_rd(bus_rd_dcache),
	207	.bus_wr(bus_wr_dcache),
	208	.bus_ready(bus_ready),
	209	);
	210	*/
	211	DCache dcache(
	212	/AUTOINST/
	213	// Outputs
	214	.dc__rw_wait_3a (dc__rw_wait_3a),
	215	.dc__rd_data_3a (dc__rd_data_3a[31:0]),
	216	.bus_req (bus_req_dcache), // Templated
	217	.bus_addr (bus_addr_dcache), // Templated
	218	.bus_wdata (bus_wdata_dcache), // Templated
	219	.bus_rd (bus_rd_dcache), // Templated
	220	.bus_wr (bus_wr_dcache), // Templated
	221	// Inputs
	222	.clk (clk), // Templated
	223	.dc__addr_3a (dc__addr_3a[31:0]),
	224	.dc__rd_req_3a (dc__rd_req_3a),
	225	.dc__wr_req_3a (dc__wr_req_3a),
	226	.dc__wr_data_3a (dc__wr_data_3a[31:0]),
	227	.bus_ack (bus_ack_dcache), // Templated
	228	.bus_rdata (bus_rdata), // Templated
	229	.bus_ready (bus_ready)); // Templated
03f45381	230
90bdd4a8 JW	231	`ifdef verilator
	232	BigBlockRAM
	233	`else
	234	BlockRAM
	235	`endif
	236	blockram(
a0bb35e7 JW	237	.clk(clk),
	238	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	239	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	240	.bus_ready(bus_ready_blockram));
	241
2bf779cf	242	/* Fetch AUTO_TEMPLATE (
2bf779cf JW	243	.jmp_0a(jmp),
2bf779cf JW	244	.jmppc_0a(jmppc),
2bf779cf JW	245	);
	246	*/
	247	Fetch fetch(
	248	/AUTOINST/
	249	// Outputs
	250	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	251	.ic__rd_req_0a (ic__rd_req_0a),
a7297aa5 JW	252	.bubble_1a (bubble_1a),
	253	.insn_1a (insn_1a[31:0]),
	254	.pc_1a (pc_1a[31:0]),
2bf779cf	255	// Inputs
a7297aa5 JW	256	.clk (clk),
a7297aa5 JW	257	.Nrst (Nrst),
2bf779cf	258	.ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99	259	.ic__rd_data_1a (ic__rd_data_1a[31:0]),
8c1ba494	260	.stall_0a (stall_0a),
2bf779cf JW	261	.jmp_0a (jmp), // Templated
2bf779cf JW	262	.jmppc_0a (jmppc)); // Templated
09e28f01	263
a7297aa5	264	/* Issue AUTO_TEMPLATE (
ae457ae9	265	.stall_1a(stall_cause_execute),
8c1ba494	266	.flush_1a(execute_out_backflush \| writeback_out_backflush),
ae457ae9	267	.cpsr_1a(writeback_out_cpsr),
a7297aa5 JW	268	);
a7297aa5 JW	269	*/
09e28f01	270	Issue issue(
a7297aa5 JW	271	/AUTOINST/
a7297aa5 JW	272	// Outputs
ae457ae9	273	.stall_0a (stall_0a),
8c1ba494 JW	274	.bubble_2a (bubble_2a),
	275	.pc_2a (pc_2a[31:0]),
	276	.insn_2a (insn_2a[31:0]),
a7297aa5 JW	277	// Inputs
	278	.clk (clk),
	279	.Nrst (Nrst),
ae457ae9	280	.stall_1a (stall_cause_execute), // Templated
8c1ba494	281	.flush_1a (execute_out_backflush \| writeback_out_backflush), // Templated
a7297aa5 JW	282	.bubble_1a (bubble_1a),
	283	.insn_1a (insn_1a[31:0]),
	284	.pc_1a (pc_1a[31:0]),
ae457ae9	285	.cpsr_1a (writeback_out_cpsr)); // Templated
90ff449a	286
a7297aa5	287	/* RegFile AUTO_TEMPLATE (
ab7ee9fc	288	.spsr(regfile_spsr),
a7297aa5 JW	289	.write(regfile_write),
	290	.write_reg(regfile_write_reg),
	291	.write_data(regfile_write_data),
	292	);
	293	*/
	294	wire [3:0] rf__read_3_4a;
	295	RegFile regfile(
	296	/AUTOINST/
	297	// Outputs
	298	.rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
	299	.rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
	300	.rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
b0e4ff00	301	.rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
a7297aa5 JW	302	.spsr (regfile_spsr), // Templated
	303	// Inputs
	304	.clk (clk),
	305	.Nrst (Nrst),
	306	.rf__read_0_1a (rf__read_0_1a[3:0]),
	307	.rf__read_1_1a (rf__read_1_1a[3:0]),
	308	.rf__read_2_1a (rf__read_2_1a[3:0]),
b0e4ff00	309	.rf__read_3_3a (rf__read_3_3a[3:0]),
a7297aa5 JW	310	.write (regfile_write), // Templated
	311	.write_reg (regfile_write_reg), // Templated
	312	.write_data (regfile_write_data)); // Templated
5ca27949	313
a7297aa5	314	/* Decode AUTO_TEMPLATE (
e74c7936	315	.stall(stall_cause_execute),
8c1ba494 JW	316	.cpsr_1a(writeback_out_cpsr),
8c1ba494 JW	317	.spsr_1a(writeback_out_spsr),
a7297aa5 JW	318	);
	319	*/
	320	Decode decode(
	321	/AUTOINST/
	322	// Outputs
8c1ba494 JW	323	.op0_2a (op0_2a[31:0]),
	324	.op1_2a (op1_2a[31:0]),
	325	.op2_2a (op2_2a[31:0]),
	326	.carry_2a (carry_2a),
	327	.cpsr_2a (cpsr_2a[31:0]),
	328	.spsr_2a (spsr_2a[31:0]),
a7297aa5 JW	329	.rf__read_0_1a (rf__read_0_1a[3:0]),
	330	.rf__read_1_1a (rf__read_1_1a[3:0]),
	331	.rf__read_2_1a (rf__read_2_1a[3:0]),
	332	// Inputs
	333	.clk (clk),
	334	.stall (stall_cause_execute), // Templated
	335	.insn_1a (insn_1a[31:0]),
	336	.pc_1a (pc_1a[31:0]),
8c1ba494 JW	337	.cpsr_1a (writeback_out_cpsr), // Templated
8c1ba494 JW	338	.spsr_1a (writeback_out_spsr), // Templated
a7297aa5 JW	339	.rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
	340	.rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
	341	.rf__rdata_2_1a (rf__rdata_2_1a[31:0]));
8c1ba494 JW	342
	343	/* Execute AUTO_TEMPLATE (
	344	.stall_2a(stall_cause_memory),
131123bc	345	.flush_2a(writeback_out_backflush),
8c1ba494	346	.outstall_2a(stall_cause_execute),
8c1ba494 JW	347	.jmp_2a(jmp_out_execute),
8c1ba494 JW	348	.jmppc_2a(jmppc_out_execute),
8c1ba494 JW	349	);
8c1ba494 JW	350	*/
bc572c5f	351	Execute execute(
8c1ba494 JW	352	/AUTOINST/
	353	// Outputs
	354	.outstall_2a (stall_cause_execute), // Templated
b0e4ff00 JW	355	.bubble_3a (bubble_3a),
	356	.cpsr_3a (cpsr_3a[31:0]),
	357	.spsr_3a (spsr_3a[31:0]),
	358	.cpsrup_3a (cpsrup_3a),
	359	.write_reg_3a (write_reg_3a),
	360	.write_num_3a (write_num_3a[3:0]),
	361	.write_data_3a (write_data_3a[31:0]),
8c1ba494 JW	362	.jmppc_2a (jmppc_out_execute), // Templated
8c1ba494 JW	363	.jmp_2a (jmp_out_execute), // Templated
b0e4ff00 JW	364	.pc_3a (pc_3a[31:0]),
	365	.insn_3a (insn_3a[31:0]),
	366	.op0_3a (op0_3a[31:0]),
	367	.op1_3a (op1_3a[31:0]),
	368	.op2_3a (op2_3a[31:0]),
8c1ba494 JW	369	// Inputs
	370	.clk (clk),
	371	.Nrst (Nrst),
	372	.stall_2a (stall_cause_memory), // Templated
131123bc	373	.flush_2a (writeback_out_backflush), // Templated
8c1ba494 JW	374	.bubble_2a (bubble_2a),
	375	.pc_2a (pc_2a[31:0]),
	376	.insn_2a (insn_2a[31:0]),
	377	.cpsr_2a (cpsr_2a[31:0]),
	378	.spsr_2a (spsr_2a[31:0]),
	379	.op0_2a (op0_2a[31:0]),
	380	.op1_2a (op1_2a[31:0]),
	381	.op2_2a (op2_2a[31:0]),
	382	.carry_2a (carry_2a));
7947b9c7	383	assign execute_out_backflush = jmp;
c65110a8	384
1d97a095	385	assign cp_insn = insn_out_execute;
b0e4ff00 JW	386	/* stall? */
	387	/* Memory AUTO_TEMPLATE (
	388	.flush(writeback_out_backflush),
b0e4ff00 JW	389	.outstall(stall_cause_memory),
	390	.outbubble(bubble_out_memory),
	391	.outpc(pc_out_memory),
	392	.outinsn(insn_out_memory),
	393	.out_write_reg(memory_out_write_reg),
	394	.out_write_num(memory_out_write_num),
43e4332c	395	.out_write_data(memory_out_write_data),
b0e4ff00 JW	396	.cp_req(cp_req),
	397	.cp_ack(cp_ack),
	398	.cp_busy(cp_busy),
	399	.cp_rnw(cp_rnw),
	400	.cp_read(cp_read),
	401	.cp_write(cp_write),
	402	.outcpsr(memory_out_cpsr),
	403	.outspsr(memory_out_spsr),
	404	.outcpsrup(memory_out_cpsrup),
	405	);
	406	*/
	407	Memory memory(
	408	/AUTOINST/
	409	// Outputs
ed1fdafe JW	410	.dc__addr_3a (dc__addr_3a[31:0]),
	411	.dc__rd_req_3a (dc__rd_req_3a),
	412	.dc__wr_req_3a (dc__wr_req_3a),
	413	.dc__wr_data_3a (dc__wr_data_3a[31:0]),
b0e4ff00 JW	414	.dc__data_size_3a (dc__data_size_3a[2:0]),
	415	.rf__read_3_3a (rf__read_3_3a[3:0]),
	416	.cp_req (cp_req), // Templated
	417	.cp_rnw (cp_rnw), // Templated
	418	.cp_write (cp_write), // Templated
	419	.outstall (stall_cause_memory), // Templated
	420	.outbubble (bubble_out_memory), // Templated
	421	.outpc (pc_out_memory), // Templated
	422	.outinsn (insn_out_memory), // Templated
	423	.out_write_reg (memory_out_write_reg), // Templated
	424	.out_write_num (memory_out_write_num), // Templated
	425	.out_write_data (memory_out_write_data), // Templated
	426	.outspsr (memory_out_spsr), // Templated
	427	.outcpsr (memory_out_cpsr), // Templated
	428	.outcpsrup (memory_out_cpsrup), // Templated
	429	// Inputs
	430	.clk (clk),
	431	.Nrst (Nrst),
	432	.flush (writeback_out_backflush), // Templated
ed1fdafe JW	433	.dc__rw_wait_3a (dc__rw_wait_3a),
ed1fdafe JW	434	.dc__rd_data_3a (dc__rd_data_3a[31:0]),
b0e4ff00 JW	435	.rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
	436	.cp_ack (cp_ack), // Templated
	437	.cp_busy (cp_busy), // Templated
	438	.cp_read (cp_read), // Templated
	439	.bubble_3a (bubble_3a),
	440	.pc_3a (pc_3a[31:0]),
	441	.insn_3a (insn_3a[31:0]),
	442	.op0_3a (op0_3a[31:0]),
	443	.op1_3a (op1_3a[31:0]),
	444	.op2_3a (op2_3a[31:0]),
	445	.spsr_3a (spsr_3a[31:0]),
	446	.cpsr_3a (cpsr_3a[31:0]),
	447	.cpsrup_3a (cpsrup_3a),
	448	.write_reg_3a (write_reg_3a),
	449	.write_num_3a (write_num_3a[3:0]),
	450	.write_data_3a (write_data_3a[31:0]));
1d97a095 JW	451
	452	Terminal terminal(
	453	.clk(clk),
	454	.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
fd003c7a JW	455	.cp_read(cp_read_terminal), .cp_write(cp_write)
	456	`ifdef verilator
	457	`else
	458	, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
	459	`endif
	460	);
ab7ee9fc JW	461
	462	Writeback writeback(
	463	.clk(clk),
	464	.inbubble(bubble_out_memory),
	465	.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897	466	.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
ab7ee9fc JW	467	.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
	468	.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
	469	.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	470	assign writeback_out_backflush = jmp_out_writeback;
149bcd1a	471
ff39dfc7	472	reg [31:0] clockno = 0;
90ff449a JW	473	always @(posedge clk)
90ff449a JW	474	begin
ff39dfc7 JW	475	clockno <= clockno + 1;
ff39dfc7 JW	476	$display("------------------------------------------------------------------------------");
a7297aa5	477	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
8c1ba494 JW	478	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
8c1ba494 JW	479	$display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
3550fbf2	480	$display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8	481	$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc	482	$display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a	483	end
ee406839	484	endmodule