added branch support, maybe
[firearm.git] / system.v
CommitLineData
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1`define BUS_ICACHE 0
2
f61f8d6f 3module System(input clk);
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4 wire [7:0] bus_req;
5 wire [7:0] bus_ack;
6 wire [31:0] bus_addr;
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7 wire [31:0] bus_rdata;
8 wire [31:0] bus_wdata;
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9 wire bus_rd, bus_wr;
10 wire bus_ready;
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11
12 wire bus_req_icache;
13 assign bus_req = {7'b0, bus_req_icache};
ee406839 14 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
45fa96c0 15
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16 wire [31:0] bus_addr_icache;
17 wire [31:0] bus_wdata_icache;
18 wire bus_rd_icache;
19 wire bus_wr_icache;
20
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21 wire [31:0] bus_rdata_blockram;
22 wire bus_ready_blockram;
23
ee406839 24 assign bus_addr = bus_addr_icache;
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25 assign bus_rdata = bus_rdata_blockram;
26 assign bus_wdata = bus_wdata_icache;
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27 assign bus_rd = bus_rd_icache;
28 assign bus_wr = bus_wr_icache;
a0bb35e7 29 assign bus_ready = bus_ready_blockram;
149bcd1a 30
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31 wire [31:0] icache_rd_addr;
32 wire icache_rd_req;
33 wire icache_rd_wait;
34 wire [31:0] icache_rd_data;
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35
36 wire stall_cause_issue;
bc572c5f 37 wire stall_cause_execute;
09e28f01 38
cb0428b6 39 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
42c1e610 40 wire decode_out_carry;
5ca27949 41 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
cb0428b6 42 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
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43 wire execute_out_stall, execute_out_bubble;
44 wire execute_out_write_reg;
45 wire [3:0] execute_out_write_num;
46 wire [31:0] execute_out_write_data;
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47 wire [31:0] jmppc;
48 wire jmp;
5ca27949 49
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50 wire bubble_out_fetch;
51 wire bubble_out_issue;
52 wire [31:0] insn_out_fetch;
53 wire [31:0] insn_out_issue;
54 wire [31:0] pc_out_fetch;
55 wire [31:0] pc_out_issue;
149bcd1a 56
ee406839 57 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
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58
59 ICache icache(
60 .clk(clk),
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61 /* XXX reset? */
62 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
63 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839 64 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7 65 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
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66 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
67 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0 68
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69 BlockRAM blockram(
70 .clk(clk),
71 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
72 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
73 .bus_ready(bus_ready_blockram));
74
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75 Fetch fetch(
76 .clk(clk),
f61f8d6f 77 .Nrst(1'b1 /* XXX */),
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78 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
79 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
149bcd1a 80 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
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81 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
82 .pc(pc_out_fetch));
83
84 Issue issue(
85 .clk(clk),
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86 .Nrst(1'b1 /* XXX */),
87 .stall(stall_cause_execute), .flush(1'b0 /* XXX */),
09e28f01 88 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
f61f8d6f 89 .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
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90 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
91 .outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a 92
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93 RegFile regfile(
94 .clk(clk),
95 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
96 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
cb0428b6 97 .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
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98
99 Decode decode(
100 .clk(clk),
cb0428b6 101 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
5ca27949 102 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
cb0428b6 103 .carry(decode_out_carry), .outspsr(decode_out_spsr),
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104 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
105 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
106
bc572c5f 107 Execute execute(
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108 .clk(clk), .Nrst(1'b0),
109 .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
bc572c5f 110 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
cb0428b6 111 .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
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112 .op2(decode_out_op2), .carry(decode_out_carry),
113 .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
114 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
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115 .write_data(execute_out_write_data),
116 .jmppc(jmppc),
117 .jmp(jmp));
118
ff39dfc7 119 reg [31:0] clockno = 0;
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120 always @(posedge clk)
121 begin
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122 clockno <= clockno + 1;
123 $display("------------------------------------------------------------------------------");
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124 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
125 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
42c1e610 126 $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
1b4fecda 127 $display("%3d: EXEC: Stall: %d, Bubble: %d, Output: %d, [%08x -> %d]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num);
90ff449a 128 end
ee406839 129endmodule
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