Fix up decode
[firearm.git] / system.v
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1`define BUS_ICACHE 0
2
5d9760a4 3module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
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4 wire [7:0] bus_req;
5 wire [7:0] bus_ack;
6 wire [31:0] bus_addr;
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7 wire [31:0] bus_rdata;
8 wire [31:0] bus_wdata;
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9 wire bus_rd, bus_wr;
10 wire bus_ready;
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11
12 wire bus_req_icache;
13 assign bus_req = {7'b0, bus_req_icache};
ee406839 14 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
45fa96c0 15
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16 wire [31:0] bus_addr_icache;
17 wire [31:0] bus_wdata_icache;
18 wire bus_rd_icache;
19 wire bus_wr_icache;
20
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21 wire [31:0] bus_rdata_blockram;
22 wire bus_ready_blockram;
23
ee406839 24 assign bus_addr = bus_addr_icache;
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25 assign bus_rdata = bus_rdata_blockram;
26 assign bus_wdata = bus_wdata_icache;
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27 assign bus_rd = bus_rd_icache;
28 assign bus_wr = bus_wr_icache;
a0bb35e7 29 assign bus_ready = bus_ready_blockram;
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30
31 wire [31:0] icache_rd_addr;
32 wire icache_rd_req;
33 wire icache_rd_wait;
34 wire [31:0] icache_rd_data;
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35
36 wire stall_cause_issue;
37
38 wire stall_in_fetch = stall_cause_issue;
39 wire stall_in_issue = 0;
40
41 wire bubble_out_fetch;
42 wire bubble_out_issue;
43 wire [31:0] insn_out_fetch;
44 wire [31:0] insn_out_issue;
45 wire [31:0] pc_out_fetch;
46 wire [31:0] pc_out_issue;
47
48 assign bubbleshield = bubble_out_issue;
49 assign insn = insn_out_issue;
50 assign pc = pc_out_issue;
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51
52 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
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53
54 ICache icache(
55 .clk(clk),
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56 /* XXX reset? */
57 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
58 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839 59 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7 60 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
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61 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
62 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0 63
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64 BlockRAM blockram(
65 .clk(clk),
66 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
67 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
68 .bus_ready(bus_ready_blockram));
69
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70 Fetch fetch(
71 .clk(clk),
72 .Nrst(1 /* XXX */),
73 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
74 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
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75 .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
76 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
77 .pc(pc_out_fetch));
78
79 Issue issue(
80 .clk(clk),
81 .Nrst(1 /* XXX */),
82 .stall(stall_in_issue), .flush(0 /* XXX */),
83 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
84 .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
85 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
86 .outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a 87
ff39dfc7 88 reg [31:0] clockno = 0;
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89 always @(posedge clk)
90 begin
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91 clockno <= clockno + 1;
92 $display("------------------------------------------------------------------------------");
93 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
94 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
90ff449a 95 end
ee406839 96endmodule
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