Add fetch module
[firearm.git] / system.v
CommitLineData
ee406839
JW
1`define BUS_ICACHE 0
2
a0bb35e7 3module System(input clk);
ee406839
JW
4 wire [7:0] bus_req;
5 wire [7:0] bus_ack;
6 wire [31:0] bus_addr;
a0bb35e7
JW
7 wire [31:0] bus_rdata;
8 wire [31:0] bus_wdata;
ee406839
JW
9 wire bus_rd, bus_wr;
10 wire bus_ready;
11
12 wire bus_req_icache = bus_req[`BUS_ICACHE];
13 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
14 wire [31:0] bus_addr_icache;
15 wire [31:0] bus_wdata_icache;
16 wire bus_rd_icache;
17 wire bus_wr_icache;
18
a0bb35e7
JW
19 wire [31:0] bus_rdata_blockram;
20 wire bus_ready_blockram;
21
ee406839 22 assign bus_addr = bus_addr_icache;
a0bb35e7
JW
23 assign bus_rdata = bus_rdata_blockram;
24 assign bus_wdata = bus_wdata_icache;
ee406839
JW
25 assign bus_rd = bus_rd_icache;
26 assign bus_wr = bus_wr_icache;
a0bb35e7 27 assign bus_ready = bus_ready_blockram;
ee406839
JW
28
29 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7
JW
30
31 ICache icache(
32 .clk(clk),
ee406839
JW
33 .rd_addr(), .rd_req(), .rd_wait(), .rd_data(),
34 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7 35 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
ee406839
JW
36 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
37 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
a0bb35e7
JW
38
39 BlockRAM blockram(
40 .clk(clk),
41 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
42 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
43 .bus_ready(bus_ready_blockram));
44
ee406839 45endmodule
This page took 0.021182 seconds and 4 git commands to generate.