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ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
authorJoshua Wise <joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 07:20:36 +0000 (02:20 -0500)
committerJoshua Wise <joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 07:20:36 +0000 (02:20 -0500)
commit3c947a993d1b35c3a15978983487617b6b56e423
tree757939ee34875ddb3982c20c90a74866fa4dd241tree | snapshot
parent26256b2698a0fc11dd9d3b11f700bf55cc1436c0commit | diff
ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency.  It hasn't been internally rerouted yet to take advantage of this; that comes next.
Fetch.v diff | blob | blame | history
ICache.v diff | blob | blame | history
system.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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