[firearm.git] / system.v

`define BUS_ICACHE 1
`define BUS_DCACHE 0

module System(input clk, input rst
`ifdef verilator
`else
	, output wire [8:0] sys_odata,
	input [8:0] sys_idata,
	output wire sys_tookdata
`endif
	);
	
	wire [7:0] bus_req;
	wire [7:0] bus_ack;
	wire [31:0] bus_addr;
	wire [31:0] bus_rdata;
	wire [31:0] bus_wdata;
	wire bus_rd, bus_wr;
	wire bus_ready;

	wire bus_req_icache;
	wire bus_req_dcache;
	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
	
	wire [31:0] bus_addr_icache;
	wire [31:0] bus_wdata_icache;
	wire bus_rd_icache;
	wire bus_wr_icache;
	
	wire [31:0] bus_addr_dcache;
	wire [31:0] bus_wdata_dcache;
	wire bus_rd_dcache;
	wire bus_wr_dcache;
	
	wire [31:0] bus_rdata_blockram;
	wire bus_ready_blockram;
	
	assign bus_addr = bus_addr_icache | bus_addr_dcache;
	assign bus_rdata = bus_rdata_blockram;
	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
	assign bus_rd = bus_rd_icache | bus_rd_dcache;
	assign bus_wr = bus_wr_icache | bus_wr_dcache;
	assign bus_ready = bus_ready_blockram;

	wire [31:0] icache_rd_addr;
	wire icache_rd_req;
	wire icache_rd_wait;
	wire [31:0] icache_rd_data;
	
	wire [31:0] dcache_addr;
	wire dcache_rd_req, dcache_wr_req;
	wire dcache_rw_wait;
	wire [31:0] dcache_wr_data, dcache_rd_data;
	
	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
	wire decode_out_carry;
	
	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	wire regfile_write;
	wire [3:0] regfile_write_reg;
	wire [31:0] regfile_write_data;
	
	wire execute_out_write_reg;
	wire [3:0] execute_out_write_num;
	wire [31:0] execute_out_write_data;
	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
	wire [31:0] execute_out_cpsr, execute_out_spsr;
	wire execute_out_cpsrup;
	
	wire jmp_out_execute, jmp_out_writeback;
	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	wire jmp = jmp_out_execute | jmp_out_writeback;
	wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
	
	wire memory_out_write_reg;
	wire [3:0] memory_out_write_num;
	wire [31:0] memory_out_write_data;
	wire [31:0] memory_out_cpsr, memory_out_spsr;
	wire memory_out_cpsrup;
	
	wire [31:0] writeback_out_cpsr, writeback_out_spsr;

	wire cp_ack_terminal;
	wire cp_busy_terminal;
	wire [31:0] cp_read_terminal;
	
	wire cp_req;
	wire [31:0] cp_insn;
	wire cp_ack = cp_ack_terminal;
	wire cp_busy = cp_busy_terminal;
	wire cp_rnw;
	wire [31:0] cp_read = cp_read_terminal;
	wire [31:0] cp_write;
	
	wire stall_cause_issue;
	wire stall_cause_execute;
	wire stall_cause_memory;
	wire bubble_out_fetch;
	wire bubble_out_issue;
	wire bubble_out_execute;
	wire bubble_out_memory;
	wire [31:0] insn_out_fetch;
	wire [31:0] insn_out_issue;
	wire [31:0] insn_out_execute;
	wire [31:0] insn_out_memory;
	wire [31:0] pc_out_fetch;
	wire [31:0] pc_out_issue;
	wire [31:0] pc_out_execute;
	wire [31:0] pc_out_memory;
	
	/*AUTOWIRE*/
	// Beginning of automatic wires (for undeclared instantiated-module outputs)
	wire [31:0]	ic__rd_addr_0a;		// From fetch of Fetch.v
	wire [31:0]	ic__rd_data_0a;		// From icache of ICache.v
	wire		ic__rd_req_0a;		// From fetch of Fetch.v
	wire		ic__rd_wait_0a;		// From icache of ICache.v
	// End of automatics

	wire execute_out_backflush;
	wire writeback_out_backflush;

	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));

	/* XXX reset? */
	/* ICache AUTO_TEMPLATE (
		.clk(clk),
		.bus_req(bus_req_icache),
		.bus_ack(bus_ack_icache),
		.bus_addr(bus_addr_icache),
		.bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_icache),
		.bus_rd(bus_rd_icache),
		.bus_wr(bus_wr_icache),
		.bus_ready(bus_ready),
		); */
	ICache icache(/*AUTOINST*/
		      // Outputs
		      .ic__rd_wait_0a	(ic__rd_wait_0a),
		      .ic__rd_data_0a	(ic__rd_data_0a[31:0]),
		      .bus_req		(bus_req_icache),	 // Templated
		      .bus_addr		(bus_addr_icache),	 // Templated
		      .bus_wdata	(bus_wdata_icache),	 // Templated
		      .bus_rd		(bus_rd_icache),	 // Templated
		      .bus_wr		(bus_wr_icache),	 // Templated
		      // Inputs
		      .clk		(clk),			 // Templated
		      .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		      .ic__rd_req_0a	(ic__rd_req_0a),
		      .bus_ack		(bus_ack_icache),	 // Templated
		      .bus_rdata	(bus_rdata),		 // Templated
		      .bus_ready	(bus_ready));		 // Templated
	
	DCache dcache(
		.clk(clk),
		.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
		.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));

`ifdef verilator
	BigBlockRAM
`else
	BlockRAM
`endif
	blockram(
		.clk(clk),
		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
		.bus_ready(bus_ready_blockram));

	/* Fetch AUTO_TEMPLATE (
		.clk(clk),
		.Nrst(~rst),
		.stall_0a(stall_cause_issue),
		.jmp_0a(jmp),
		.jmppc_0a(jmppc),
		.bubble_1a(bubble_out_fetch),
		.insn_1a(insn_out_fetch),
		.pc_1a(pc_out_fetch),
		);
	*/
	Fetch fetch(
		/*AUTOINST*/
		    // Outputs
		    .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		    .ic__rd_req_0a	(ic__rd_req_0a),
		    .bubble_1a		(bubble_out_fetch),	 // Templated
		    .insn_1a		(insn_out_fetch),	 // Templated
		    .pc_1a		(pc_out_fetch),		 // Templated
		    // Inputs
		    .clk		(clk),			 // Templated
		    .Nrst		(~rst),			 // Templated
		    .ic__rd_wait_0a	(ic__rd_wait_0a),
		    .ic__rd_data_0a	(ic__rd_data_0a[31:0]),
		    .stall_0a		(stall_cause_issue),	 // Templated
		    .jmp_0a		(jmp),			 // Templated
		    .jmppc_0a		(jmppc));		 // Templated
	
	Issue issue(
		.clk(clk),
		.Nrst(~rst),
		.stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
		.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
		.inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
		.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
		.outpc(pc_out_issue), .outinsn(insn_out_issue));
	
	RegFile regfile(
		.clk(clk), .Nrst(~rst),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
		.spsr(regfile_spsr),
		.write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
	
	Decode decode(
		.clk(clk),
		.stall(stall_cause_execute),
		.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
		.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
		.carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	
	Execute execute(
		.clk(clk), .Nrst(~rst),
		.stall(stall_cause_memory), .flush(writeback_out_backflush),
		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
		.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
		.op2(decode_out_op2), .carry(decode_out_carry),
		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
		.write_data(execute_out_write_data),
		.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
		.outpc(pc_out_execute), .outinsn(insn_out_execute),
		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
		.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
	assign execute_out_backflush = jmp;
	
	assign cp_insn = insn_out_execute;
	Memory memory(
		.clk(clk), .Nrst(~rst),
		/* stall? */ .flush(writeback_out_backflush),
		.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
		.spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
		.outpc(pc_out_memory), .outinsn(insn_out_memory),
		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
		.out_write_data(memory_out_write_data),
		.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
		.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
	
	Terminal terminal(	
		.clk(clk),
		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
		.cp_read(cp_read_terminal), .cp_write(cp_write)
`ifdef verilator
`else
		, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
`endif
		);
	
	Writeback writeback(
		.clk(clk),
		.inbubble(bubble_out_memory),
		.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
		.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
		.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
		.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	assign writeback_out_backflush = jmp_out_writeback;

	reg [31:0] clockno = 0;
	always @(posedge clk)
	begin
		clockno <= clockno + 1;
		$display("------------------------------------------------------------------------------");
		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
	end
endmodule
Commit	Line	Data
e3a9107a JW	1	`define BUS_ICACHE 1
e3a9107a JW	2	`define BUS_DCACHE 0
ee406839	3
a4f724e6	4	module System(input clk, input rst
fd003c7a JW	5	`ifdef verilator
	6	`else
	7	, output wire [8:0] sys_odata,
	8	input [8:0] sys_idata,
	9	output wire sys_tookdata
	10	`endif
	11	);
	12
ee406839 JW	13	wire [7:0] bus_req;
	14	wire [7:0] bus_ack;
	15	wire [31:0] bus_addr;
a0bb35e7 JW	16	wire [31:0] bus_rdata;
a0bb35e7 JW	17	wire [31:0] bus_wdata;
ee406839 JW	18	wire bus_rd, bus_wr;
ee406839 JW	19	wire bus_ready;
45fa96c0	20
03f45381 JW	21	wire bus_req_icache;
03f45381 JW	22	wire bus_req_dcache;
e3a9107a	23	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839	24	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381	25	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0	26
ee406839 JW	27	wire [31:0] bus_addr_icache;
	28	wire [31:0] bus_wdata_icache;
	29	wire bus_rd_icache;
	30	wire bus_wr_icache;
	31
03f45381 JW	32	wire [31:0] bus_addr_dcache;
	33	wire [31:0] bus_wdata_dcache;
	34	wire bus_rd_dcache;
	35	wire bus_wr_dcache;
	36
a0bb35e7 JW	37	wire [31:0] bus_rdata_blockram;
	38	wire bus_ready_blockram;
	39
03f45381	40	assign bus_addr = bus_addr_icache \| bus_addr_dcache;
a0bb35e7	41	assign bus_rdata = bus_rdata_blockram;
03f45381 JW	42	assign bus_wdata = bus_wdata_icache \| bus_wdata_dcache;
	43	assign bus_rd = bus_rd_icache \| bus_rd_dcache;
	44	assign bus_wr = bus_wr_icache \| bus_wr_dcache;
a0bb35e7	45	assign bus_ready = bus_ready_blockram;
149bcd1a	46
5d9760a4 JW	47	wire [31:0] icache_rd_addr;
	48	wire icache_rd_req;
	49	wire icache_rd_wait;
	50	wire [31:0] icache_rd_data;
09e28f01	51
03f45381 JW	52	wire [31:0] dcache_addr;
	53	wire dcache_rd_req, dcache_wr_req;
	54	wire dcache_rw_wait;
	55	wire [31:0] dcache_wr_data, dcache_rd_data;
	56
ab7ee9fc	57	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610	58	wire decode_out_carry;
c65110a8 JW	59
	60	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	61	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
ab7ee9fc JW	62	wire regfile_write;
	63	wire [3:0] regfile_write_reg;
	64	wire [31:0] regfile_write_data;
c65110a8	65
bc572c5f JW	66	wire execute_out_write_reg;
	67	wire [3:0] execute_out_write_num;
	68	wire [31:0] execute_out_write_data;
c65110a8	69	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1	70	wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897	71	wire execute_out_cpsrup;
ab7ee9fc JW	72
	73	wire jmp_out_execute, jmp_out_writeback;
	74	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	75	wire jmp = jmp_out_execute \| jmp_out_writeback;
	76	wire [31:0] jmppc = jmppc_out_execute \| jmppc_out_writeback;
5ca27949	77
c65110a8 JW	78	wire memory_out_write_reg;
	79	wire [3:0] memory_out_write_num;
	80	wire [31:0] memory_out_write_data;
ab7ee9fc	81	wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897	82	wire memory_out_cpsrup;
ab7ee9fc JW	83
ab7ee9fc JW	84	wire [31:0] writeback_out_cpsr, writeback_out_spsr;
1d97a095 JW	85
	86	wire cp_ack_terminal;
	87	wire cp_busy_terminal;
	88	wire [31:0] cp_read_terminal;
c65110a8	89
43e4332c	90	wire cp_req;
1d97a095 JW	91	wire [31:0] cp_insn;
	92	wire cp_ack = cp_ack_terminal;
	93	wire cp_busy = cp_busy_terminal;
43e4332c	94	wire cp_rnw;
1d97a095	95	wire [31:0] cp_read = cp_read_terminal;
43e4332c JW	96	wire [31:0] cp_write;
43e4332c JW	97
c65110a8 JW	98	wire stall_cause_issue;
	99	wire stall_cause_execute;
	100	wire stall_cause_memory;
09e28f01 JW	101	wire bubble_out_fetch;
09e28f01 JW	102	wire bubble_out_issue;
2393422a	103	wire bubble_out_execute;
c65110a8	104	wire bubble_out_memory;
09e28f01 JW	105	wire [31:0] insn_out_fetch;
09e28f01 JW	106	wire [31:0] insn_out_issue;
2393422a	107	wire [31:0] insn_out_execute;
c65110a8	108	wire [31:0] insn_out_memory;
09e28f01 JW	109	wire [31:0] pc_out_fetch;
09e28f01 JW	110	wire [31:0] pc_out_issue;
2393422a	111	wire [31:0] pc_out_execute;
c65110a8	112	wire [31:0] pc_out_memory;
2bf779cf JW	113
	114	/AUTOWIRE/
	115	// Beginning of automatic wires (for undeclared instantiated-module outputs)
	116	wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
	117	wire [31:0] ic__rd_data_0a; // From icache of ICache.v
	118	wire ic__rd_req_0a; // From fetch of Fetch.v
	119	wire ic__rd_wait_0a; // From icache of ICache.v
	120	// End of automatics
149bcd1a	121
7947b9c7	122	wire execute_out_backflush;
ab7ee9fc	123	wire writeback_out_backflush;
c2b9d4b7	124
ee406839	125	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7	126
2bf779cf JW	127	/* XXX reset? */
2bf779cf JW	128	/* ICache AUTO_TEMPLATE (
a0bb35e7	129	.clk(clk),
2bf779cf JW	130	.bus_req(bus_req_icache),
	131	.bus_ack(bus_ack_icache),
	132	.bus_addr(bus_addr_icache),
	133	.bus_rdata(bus_rdata),
	134	.bus_wdata(bus_wdata_icache),
	135	.bus_rd(bus_rd_icache),
	136	.bus_wr(bus_wr_icache),
	137	.bus_ready(bus_ready),
	138	); */
	139	ICache icache(/AUTOINST/
	140	// Outputs
	141	.ic__rd_wait_0a (ic__rd_wait_0a),
	142	.ic__rd_data_0a (ic__rd_data_0a[31:0]),
	143	.bus_req (bus_req_icache), // Templated
	144	.bus_addr (bus_addr_icache), // Templated
	145	.bus_wdata (bus_wdata_icache), // Templated
	146	.bus_rd (bus_rd_icache), // Templated
	147	.bus_wr (bus_wr_icache), // Templated
	148	// Inputs
	149	.clk (clk), // Templated
	150	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	151	.ic__rd_req_0a (ic__rd_req_0a),
	152	.bus_ack (bus_ack_icache), // Templated
	153	.bus_rdata (bus_rdata), // Templated
	154	.bus_ready (bus_ready)); // Templated
45fa96c0	155
03f45381 JW	156	DCache dcache(
	157	.clk(clk),
	158	.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
	159	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
	160	.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
	161	.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
	162	.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
	163	.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
	164
90bdd4a8 JW	165	`ifdef verilator
	166	BigBlockRAM
	167	`else
	168	BlockRAM
	169	`endif
	170	blockram(
a0bb35e7 JW	171	.clk(clk),
	172	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	173	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	174	.bus_ready(bus_ready_blockram));
	175
2bf779cf	176	/* Fetch AUTO_TEMPLATE (
5d9760a4	177	.clk(clk),
a4f724e6	178	.Nrst(~rst),
2bf779cf JW	179	.stall_0a(stall_cause_issue),
	180	.jmp_0a(jmp),
	181	.jmppc_0a(jmppc),
	182	.bubble_1a(bubble_out_fetch),
	183	.insn_1a(insn_out_fetch),
	184	.pc_1a(pc_out_fetch),
	185	);
	186	*/
	187	Fetch fetch(
	188	/AUTOINST/
	189	// Outputs
	190	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	191	.ic__rd_req_0a (ic__rd_req_0a),
	192	.bubble_1a (bubble_out_fetch), // Templated
	193	.insn_1a (insn_out_fetch), // Templated
	194	.pc_1a (pc_out_fetch), // Templated
	195	// Inputs
	196	.clk (clk), // Templated
	197	.Nrst (~rst), // Templated
	198	.ic__rd_wait_0a (ic__rd_wait_0a),
	199	.ic__rd_data_0a (ic__rd_data_0a[31:0]),
	200	.stall_0a (stall_cause_issue), // Templated
	201	.jmp_0a (jmp), // Templated
	202	.jmppc_0a (jmppc)); // Templated
09e28f01 JW	203
	204	Issue issue(
	205	.clk(clk),
a4f724e6	206	.Nrst(~rst),
ab7ee9fc	207	.stall(stall_cause_execute), .flush(execute_out_backflush \| writeback_out_backflush),
09e28f01	208	.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
ab7ee9fc	209	.inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
09e28f01 JW	210	.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
09e28f01 JW	211	.outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a	212
5ca27949	213	RegFile regfile(
a4f724e6	214	.clk(clk), .Nrst(~rst),
8077f6bb JW	215	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
8077f6bb JW	216	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
ab7ee9fc JW	217	.spsr(regfile_spsr),
ab7ee9fc JW	218	.write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
5ca27949 JW	219
	220	Decode decode(
	221	.clk(clk),
e74c7936	222	.stall(stall_cause_execute),
ab7ee9fc	223	.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
5ca27949	224	.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
ab7ee9fc	225	.carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
5ca27949 JW	226	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
	227	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	228
bc572c5f	229	Execute execute(
a4f724e6	230	.clk(clk), .Nrst(~rst),
ab7ee9fc	231	.stall(stall_cause_memory), .flush(writeback_out_backflush),
bc572c5f	232	.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
ab7ee9fc	233	.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
bc572c5f	234	.op2(decode_out_op2), .carry(decode_out_carry),
2393422a	235	.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
bc572c5f	236	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
149bcd1a	237	.write_data(execute_out_write_data),
ab7ee9fc	238	.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
c65110a8	239	.outpc(pc_out_execute), .outinsn(insn_out_execute),
1e66d5d1	240	.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
fdecc897	241	.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
7947b9c7	242	assign execute_out_backflush = jmp;
c65110a8	243
1d97a095	244	assign cp_insn = insn_out_execute;
c65110a8	245	Memory memory(
a4f724e6	246	.clk(clk), .Nrst(~rst),
ab7ee9fc	247	/* stall? */ .flush(writeback_out_backflush),
b455d481 JW	248	.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
b455d481 JW	249	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
c65110a8 JW	250	.st_read(regfile_read_3), .st_data(regfile_rdata_3),
	251	.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
	252	.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
fdecc897	253	.spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
c65110a8 JW	254	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
	255	.outstall(stall_cause_memory), .outbubble(bubble_out_memory),
	256	.outpc(pc_out_memory), .outinsn(insn_out_memory),
	257	.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
43e4332c	258	.out_write_data(memory_out_write_data),
ab7ee9fc	259	.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
fdecc897	260	.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
1d97a095 JW	261
	262	Terminal terminal(
	263	.clk(clk),
	264	.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
fd003c7a JW	265	.cp_read(cp_read_terminal), .cp_write(cp_write)
	266	`ifdef verilator
	267	`else
	268	, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
	269	`endif
	270	);
ab7ee9fc JW	271
	272	Writeback writeback(
	273	.clk(clk),
	274	.inbubble(bubble_out_memory),
	275	.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897	276	.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
ab7ee9fc JW	277	.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
	278	.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
	279	.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	280	assign writeback_out_backflush = jmp_out_writeback;
149bcd1a	281
ff39dfc7	282	reg [31:0] clockno = 0;
90ff449a JW	283	always @(posedge clk)
90ff449a JW	284	begin
ff39dfc7 JW	285	clockno <= clockno + 1;
ff39dfc7 JW	286	$display("------------------------------------------------------------------------------");
5ca27949 JW	287	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
5ca27949 JW	288	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
db2351c4	289	$display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
3550fbf2	290	$display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8	291	$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc	292	$display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a	293	end
ee406839	294	endmodule