Actually do the issue???
[firearm.git] / system.v
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1`define BUS_ICACHE 0
2
5d9760a4 3module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
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4 wire [7:0] bus_req;
5 wire [7:0] bus_ack;
6 wire [31:0] bus_addr;
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7 wire [31:0] bus_rdata;
8 wire [31:0] bus_wdata;
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9 wire bus_rd, bus_wr;
10 wire bus_ready;
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11
12 wire bus_req_icache;
13 assign bus_req = {7'b0, bus_req_icache};
ee406839 14 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
45fa96c0 15
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16 wire [31:0] bus_addr_icache;
17 wire [31:0] bus_wdata_icache;
18 wire bus_rd_icache;
19 wire bus_wr_icache;
20
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21 wire [31:0] bus_rdata_blockram;
22 wire bus_ready_blockram;
23
ee406839 24 assign bus_addr = bus_addr_icache;
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25 assign bus_rdata = bus_rdata_blockram;
26 assign bus_wdata = bus_wdata_icache;
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27 assign bus_rd = bus_rd_icache;
28 assign bus_wr = bus_wr_icache;
a0bb35e7 29 assign bus_ready = bus_ready_blockram;
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30
31 wire [31:0] icache_rd_addr;
32 wire icache_rd_req;
33 wire icache_rd_wait;
34 wire [31:0] icache_rd_data;
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35
36 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
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37
38 ICache icache(
39 .clk(clk),
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40 /* XXX reset? */
41 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
42 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839 43 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7 44 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
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45 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
46 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0 47
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48 BlockRAM blockram(
49 .clk(clk),
50 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
51 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
52 .bus_ready(bus_ready_blockram));
53
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54 Fetch fetch(
55 .clk(clk),
56 .Nrst(1 /* XXX */),
57 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
58 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
59 .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
60 .bubble(bubbleshield), .insn(insn), .pc(pc));
61
ee406839 62endmodule
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