[firearm.git] / system.v

`define BUS_ICACHE 0
`define BUS_DCACHE 1

module System(input clk);
	wire [7:0] bus_req;
	wire [7:0] bus_ack;
	wire [31:0] bus_addr;
	wire [31:0] bus_rdata;
	wire [31:0] bus_wdata;
	wire bus_rd, bus_wr;
	wire bus_ready;

	wire bus_req_icache;
	wire bus_req_dcache;
	assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
	
	wire [31:0] bus_addr_icache;
	wire [31:0] bus_wdata_icache;
	wire bus_rd_icache;
	wire bus_wr_icache;
	
	wire [31:0] bus_addr_dcache;
	wire [31:0] bus_wdata_dcache;
	wire bus_rd_dcache;
	wire bus_wr_dcache;
	
	wire [31:0] bus_rdata_blockram;
	wire bus_ready_blockram;
	
	assign bus_addr = bus_addr_icache | bus_addr_dcache;
	assign bus_rdata = bus_rdata_blockram;
	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
	assign bus_rd = bus_rd_icache | bus_rd_dcache;
	assign bus_wr = bus_wr_icache | bus_wr_dcache;
	assign bus_ready = bus_ready_blockram;

	wire [31:0] icache_rd_addr;
	wire icache_rd_req;
	wire icache_rd_wait;
	wire [31:0] icache_rd_data;
	
	wire [31:0] dcache_addr;
	wire dcache_rd_req, dcache_wr_req;
	wire dcache_rw_wait;
	wire [31:0] dcache_wr_data, dcache_rd_data;
	
	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
	wire decode_out_carry;
	
	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	
	wire execute_out_write_reg;
	wire [3:0] execute_out_write_num;
	wire [31:0] execute_out_write_data;
	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
	wire [31:0] jmppc;
	wire jmp;
	
	wire memory_out_write_reg;
	wire [3:0] memory_out_write_num;
	wire [31:0] memory_out_write_data;
	
	wire stall_cause_issue;
	wire stall_cause_execute;
	wire stall_cause_memory;
	wire bubble_out_fetch;
	wire bubble_out_issue;
	wire bubble_out_execute;
	wire bubble_out_memory;
	wire [31:0] insn_out_fetch;
	wire [31:0] insn_out_issue;
	wire [31:0] insn_out_execute;
	wire [31:0] insn_out_memory;
	wire [31:0] pc_out_fetch;
	wire [31:0] pc_out_issue;
	wire [31:0] pc_out_execute;
	wire [31:0] pc_out_memory;

	wire execute_out_backflush;

	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));

	ICache icache(
		.clk(clk),
		/* XXX reset? */
		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
		.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
		.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
		.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
	
	DCache dcache(
		.clk(clk),
		.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
		.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));

	BlockRAM blockram(
		.clk(clk),
		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
		.bus_ready(bus_ready_blockram));

	Fetch fetch(
		.clk(clk),
		.Nrst(1'b1 /* XXX */),
		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
		.stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
		.bubble(bubble_out_fetch), .insn(insn_out_fetch),
		.pc(pc_out_fetch));
	
	Issue issue(
		.clk(clk),
		.Nrst(1'b1 /* XXX */),
		.stall(stall_cause_execute), .flush(execute_out_backflush),
		.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
		.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
		.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
		.outpc(pc_out_issue), .outinsn(insn_out_issue));
	
	RegFile regfile(
		.clk(clk),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
		.spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
	
	Decode decode(
		.clk(clk),
		.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
		.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
		.carry(decode_out_carry), .outspsr(decode_out_spsr),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	
	Execute execute(
		.clk(clk), .Nrst(1'b0),
		.stall(stall_cause_memory), .flush(1'b0),
		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
		.op2(decode_out_op2), .carry(decode_out_carry),
		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
		.write_data(execute_out_write_data),
		.jmp(jmp), .jmppc(jmppc),
		.outpc(pc_out_execute), .outinsn(insn_out_execute),
		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2));
	assign execute_out_backflush = jmp;
	
	Memory memory(
		.clk(clk), .Nrst(1'b0),
		/* stall? flush? */
		.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
		.outpc(pc_out_memory), .outinsn(insn_out_memory),
		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
		.out_write_data(memory_out_write_data));

	reg [31:0] clockno = 0;
	always @(posedge clk)
	begin
		clockno <= clockno + 1;
		$display("------------------------------------------------------------------------------");
		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
		$display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
	end
endmodule
Commit	Line	Data
ee406839	1	`define BUS_ICACHE 0
03f45381	2	`define BUS_DCACHE 1
ee406839	3
f61f8d6f	4	module System(input clk);
ee406839 JW	5	wire [7:0] bus_req;
	6	wire [7:0] bus_ack;
	7	wire [31:0] bus_addr;
a0bb35e7 JW	8	wire [31:0] bus_rdata;
a0bb35e7 JW	9	wire [31:0] bus_wdata;
ee406839 JW	10	wire bus_rd, bus_wr;
ee406839 JW	11	wire bus_ready;
45fa96c0	12
03f45381 JW	13	wire bus_req_icache;
	14	wire bus_req_dcache;
	15	assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
ee406839	16	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381	17	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0	18
ee406839 JW	19	wire [31:0] bus_addr_icache;
	20	wire [31:0] bus_wdata_icache;
	21	wire bus_rd_icache;
	22	wire bus_wr_icache;
	23
03f45381 JW	24	wire [31:0] bus_addr_dcache;
	25	wire [31:0] bus_wdata_dcache;
	26	wire bus_rd_dcache;
	27	wire bus_wr_dcache;
	28
a0bb35e7 JW	29	wire [31:0] bus_rdata_blockram;
	30	wire bus_ready_blockram;
	31
03f45381	32	assign bus_addr = bus_addr_icache \| bus_addr_dcache;
a0bb35e7	33	assign bus_rdata = bus_rdata_blockram;
03f45381 JW	34	assign bus_wdata = bus_wdata_icache \| bus_wdata_dcache;
	35	assign bus_rd = bus_rd_icache \| bus_rd_dcache;
	36	assign bus_wr = bus_wr_icache \| bus_wr_dcache;
a0bb35e7	37	assign bus_ready = bus_ready_blockram;
149bcd1a	38
5d9760a4 JW	39	wire [31:0] icache_rd_addr;
	40	wire icache_rd_req;
	41	wire icache_rd_wait;
	42	wire [31:0] icache_rd_data;
09e28f01	43
03f45381 JW	44	wire [31:0] dcache_addr;
	45	wire dcache_rd_req, dcache_wr_req;
	46	wire dcache_rw_wait;
	47	wire [31:0] dcache_wr_data, dcache_rd_data;
	48
cb0428b6	49	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
42c1e610	50	wire decode_out_carry;
c65110a8 JW	51
	52	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	53	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	54
bc572c5f JW	55	wire execute_out_write_reg;
	56	wire [3:0] execute_out_write_num;
	57	wire [31:0] execute_out_write_data;
c65110a8	58	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
149bcd1a CL	59	wire [31:0] jmppc;
149bcd1a CL	60	wire jmp;
5ca27949	61
c65110a8 JW	62	wire memory_out_write_reg;
	63	wire [3:0] memory_out_write_num;
	64	wire [31:0] memory_out_write_data;
	65
	66	wire stall_cause_issue;
	67	wire stall_cause_execute;
	68	wire stall_cause_memory;
09e28f01 JW	69	wire bubble_out_fetch;
09e28f01 JW	70	wire bubble_out_issue;
2393422a	71	wire bubble_out_execute;
c65110a8	72	wire bubble_out_memory;
09e28f01 JW	73	wire [31:0] insn_out_fetch;
09e28f01 JW	74	wire [31:0] insn_out_issue;
2393422a	75	wire [31:0] insn_out_execute;
c65110a8	76	wire [31:0] insn_out_memory;
09e28f01 JW	77	wire [31:0] pc_out_fetch;
09e28f01 JW	78	wire [31:0] pc_out_issue;
2393422a	79	wire [31:0] pc_out_execute;
c65110a8	80	wire [31:0] pc_out_memory;
149bcd1a	81
7947b9c7	82	wire execute_out_backflush;
c2b9d4b7	83
ee406839	84	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7 JW	85
	86	ICache icache(
	87	.clk(clk),
5d9760a4 JW	88	/* XXX reset? */
	89	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
	90	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839	91	.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7	92	.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
ee406839 JW	93	.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
ee406839 JW	94	.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0	95
03f45381 JW	96	DCache dcache(
	97	.clk(clk),
	98	.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
	99	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
	100	.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
	101	.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
	102	.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
	103	.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
	104
a0bb35e7 JW	105	BlockRAM blockram(
	106	.clk(clk),
	107	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	108	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	109	.bus_ready(bus_ready_blockram));
	110
5d9760a4 JW	111	Fetch fetch(
5d9760a4 JW	112	.clk(clk),
f61f8d6f	113	.Nrst(1'b1 /* XXX */),
5d9760a4 JW	114	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
5d9760a4 JW	115	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
149bcd1a	116	.stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
09e28f01 JW	117	.bubble(bubble_out_fetch), .insn(insn_out_fetch),
	118	.pc(pc_out_fetch));
	119
	120	Issue issue(
	121	.clk(clk),
f61f8d6f	122	.Nrst(1'b1 /* XXX */),
7947b9c7	123	.stall(stall_cause_execute), .flush(execute_out_backflush),
09e28f01	124	.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
f61f8d6f	125	.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
09e28f01 JW	126	.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
09e28f01 JW	127	.outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a	128
5ca27949 JW	129	RegFile regfile(
5ca27949 JW	130	.clk(clk),
c65110a8 JW	131	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
c65110a8 JW	132	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
cb0428b6	133	.spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
5ca27949 JW	134
	135	Decode decode(
	136	.clk(clk),
cb0428b6	137	.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
5ca27949	138	.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
cb0428b6	139	.carry(decode_out_carry), .outspsr(decode_out_spsr),
5ca27949 JW	140	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
	141	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	142
bc572c5f	143	Execute execute(
f61f8d6f	144	.clk(clk), .Nrst(1'b0),
c65110a8	145	.stall(stall_cause_memory), .flush(1'b0),
bc572c5f	146	.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
cb0428b6	147	.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
bc572c5f	148	.op2(decode_out_op2), .carry(decode_out_carry),
2393422a	149	.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
bc572c5f	150	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
149bcd1a	151	.write_data(execute_out_write_data),
2393422a	152	.jmp(jmp), .jmppc(jmppc),
c65110a8 JW	153	.outpc(pc_out_execute), .outinsn(insn_out_execute),
c65110a8 JW	154	.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2));
7947b9c7	155	assign execute_out_backflush = jmp;
c65110a8 JW	156
	157	Memory memory(
	158	.clk(clk), .Nrst(1'b0),
	159	/* stall? flush? */
b455d481 JW	160	.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
b455d481 JW	161	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
c65110a8 JW	162	.st_read(regfile_read_3), .st_data(regfile_rdata_3),
	163	.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
	164	.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
	165	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
	166	.outstall(stall_cause_memory), .outbubble(bubble_out_memory),
	167	.outpc(pc_out_memory), .outinsn(insn_out_memory),
	168	.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
	169	.out_write_data(memory_out_write_data));
149bcd1a	170
ff39dfc7	171	reg [31:0] clockno = 0;
90ff449a JW	172	always @(posedge clk)
90ff449a JW	173	begin
ff39dfc7 JW	174	clockno <= clockno + 1;
ff39dfc7 JW	175	$display("------------------------------------------------------------------------------");
5ca27949 JW	176	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
5ca27949 JW	177	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
42c1e610	178	$display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
2393422a	179	$display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
c65110a8	180	$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
90ff449a	181	end
ee406839	182	endmodule