Ok, move read_0, read_1, read_2 back into a unified block again.
[firearm.git] / system.v
CommitLineData
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1`define BUS_ICACHE 0
2
5d9760a4 3module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
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4 wire [7:0] bus_req;
5 wire [7:0] bus_ack;
6 wire [31:0] bus_addr;
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7 wire [31:0] bus_rdata;
8 wire [31:0] bus_wdata;
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9 wire bus_rd, bus_wr;
10 wire bus_ready;
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11
12 wire bus_req_icache;
13 assign bus_req = {7'b0, bus_req_icache};
ee406839 14 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
45fa96c0 15
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16 wire [31:0] bus_addr_icache;
17 wire [31:0] bus_wdata_icache;
18 wire bus_rd_icache;
19 wire bus_wr_icache;
20
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21 wire [31:0] bus_rdata_blockram;
22 wire bus_ready_blockram;
23
ee406839 24 assign bus_addr = bus_addr_icache;
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25 assign bus_rdata = bus_rdata_blockram;
26 assign bus_wdata = bus_wdata_icache;
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27 assign bus_rd = bus_rd_icache;
28 assign bus_wr = bus_wr_icache;
a0bb35e7 29 assign bus_ready = bus_ready_blockram;
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30
31 wire [31:0] icache_rd_addr;
32 wire icache_rd_req;
33 wire icache_rd_wait;
34 wire [31:0] icache_rd_data;
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35
36 wire stall_cause_issue;
37
38 wire stall_in_fetch = stall_cause_issue;
39 wire stall_in_issue = 0;
40
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41 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr;
42 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
43 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
44
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45 wire bubble_out_fetch;
46 wire bubble_out_issue;
47 wire [31:0] insn_out_fetch;
48 wire [31:0] insn_out_issue;
49 wire [31:0] pc_out_fetch;
50 wire [31:0] pc_out_issue;
51
52 assign bubbleshield = bubble_out_issue;
53 assign insn = insn_out_issue;
54 assign pc = pc_out_issue;
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55
56 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
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57
58 ICache icache(
59 .clk(clk),
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60 /* XXX reset? */
61 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
62 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839 63 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7 64 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
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65 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
66 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0 67
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68 BlockRAM blockram(
69 .clk(clk),
70 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
71 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
72 .bus_ready(bus_ready_blockram));
73
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74 Fetch fetch(
75 .clk(clk),
76 .Nrst(1 /* XXX */),
77 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
78 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
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79 .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
80 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
81 .pc(pc_out_fetch));
82
83 Issue issue(
84 .clk(clk),
85 .Nrst(1 /* XXX */),
86 .stall(stall_in_issue), .flush(0 /* XXX */),
87 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
88 .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
89 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
90 .outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a 91
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92 RegFile regfile(
93 .clk(clk),
94 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
95 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
96 .write(0), .write_req(0), .write_data(0 /* XXX */));
97
98 Decode decode(
99 .clk(clk),
100 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
101 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
102 .outcpsr(decode_out_cpsr),
103 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
104 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
105
ff39dfc7 106 reg [31:0] clockno = 0;
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107 always @(posedge clk)
108 begin
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109 clockno <= clockno + 1;
110 $display("------------------------------------------------------------------------------");
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111 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
112 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
113 $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, cpsr %08x", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr);
90ff449a 114 end
ee406839 115endmodule
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