[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	input flush,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,
	output reg [2:0] data_size,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output reg cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input cpsrup,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] outspsr = 32'hxxxxxxxx,
	output reg [31:0] outcpsr = 32'hxxxxxxxx,
	output reg outcpsrup = 1'hx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg next_outcpsrup;
	reg [31:0] prevaddr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;

	reg next_outbubble;	
	reg next_write_reg;
	reg [3:0] next_write_num;
	reg [31:0] next_write_data;

	reg [3:0] lsr_state = 4'b0001, next_lsr_state;
	reg [31:0] align_s1, align_s2, align_rddata;

	reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
	reg [31:0] lsrh_rddata;
	reg [15:0] lsrh_rddata_s1;
	reg [7:0] lsrh_rddata_s2;

	reg [15:0] regs, next_regs;
	reg [3:0] lsm_state = 4'b0001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;
	
	reg do_rd_data_latch;
	reg [31:0] rd_data_latch = 32'hxxxxxxxx;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		if (!rw_wait)
			prev_offset <= offset;
		prev_raddr <= raddr;
		outcpsr <= next_outcpsr;
		outspsr <= spsr;
		outcpsrup <= next_outcpsrup;
		swp_state <= next_swp_state;
		lsm_state <= next_lsm_state;
		lsr_state <= next_lsr_state;
		lsrh_state <= next_lsrh_state;
		if (do_rd_data_latch)
			rd_data_latch <= rd_data;
		prevaddr <= addr;
	end
	
	reg delayedflush = 0;
	always @(posedge clk)
		if (flush && outstall /* halp! I can't do it now, maybe later? */)
			delayedflush <= 1;
		else if (!outstall /* anything has been handled this time around */)
			delayedflush <= 0;

	always @(*)
	begin
		addr = prevaddr;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		data_size = 3'bxxx;
		outstall = 1'b0;
		do_rd_data_latch = 0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
		next_outcpsrup = cpsrup;
		lsrh_rddata = 32'hxxxxxxxx;
		lsrh_rddata_s1 = 16'hxxxx;
		lsrh_rddata_s2 = 8'hxx;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_lsrh_state = lsrh_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		/* XXX shit not given about endianness */
		casez(insn)
		`DECODE_ALU_SWP: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			busaddr = {op0[31:2], 2'b0};
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(swp_state)
			2'b01: begin
				rd_req = 1'b1;
				outstall = 1'b1;
				if(!rw_wait) begin
					next_swp_state = 2'b10;
					next_swp_oldval = rd_data;
				end
				$display("SWP: read stage");
			end
			2'b10: begin
				wr_req = 1'b1;
				wr_data = insn[22] ? {4{op1[7:0]}} : op1;
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
				if(!rw_wait)
					next_swp_state = 2'b01;
				$display("SWP: write stage");
			end
			default: begin end
			endcase
		end
		`DECODE_ALU_MULT: begin end
		`DECODE_ALU_HDATA_REG,
		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			case(insn[6:5])
			2'b00: begin end /* swp */
			2'b01: begin /* unsigned half */
				wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
				data_size = 3'b010;
				lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
			end
			2'b10: begin /* signed byte */
				wr_data = {4{op2[7:0]}};
				data_size = 3'b001;
				lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
				lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
				lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
			end
			2'b11: begin /* signed half */
				wr_data = {2{op2[15:0]}};
				data_size = 3'b010;
				lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
			end
			endcase

			case(lsrh_state)
			3'b001: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_num = insn[15:12];
				next_write_data = lsrh_rddata;
				if(insn[20]) begin
					next_write_reg = 1'b1;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsrh_state = 3'b010;
				end
				$display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
			end
			3'b010: begin
				next_outbubble = 1'b0;
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsrh_state = 3'b100;
			end
			3'b100: begin
				outstall = 0;
				next_lsrh_state = 3'b001;
			end
			default: begin end
			endcase
			
			if ((lsrh_state == 3'b001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsrh_state = 3'b001;
			end
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? addr : op0; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
			/* select byte or word */
			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
			wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(lsr_state)
			4'b0001: begin
				rd_req = insn[20] /* L */ || insn[22] /* B */;
				wr_req = !insn[20] /* L */ && !insn[22]/* B */;
				next_write_reg = insn[20] /* L */;
				next_write_num = insn[15:12];
				if(insn[20] /* L */) begin
					next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
				end
				if (insn[22] /* B */ && !insn[20] /* L */) begin
					do_rd_data_latch = 1;
					outstall = 1'b1;
					if (!rw_wait)
						next_lsr_state = 4'b0010;	/* XXX: One-hot, my ass. */
				end else if(insn[21] /* W */ | !insn[24] /* P */) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsr_state = 4'b0100;
				end
				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
			end
			4'b0010: begin
				$display("LDRSTR: Handling STRB");
				outstall = 1;
				rd_req = 0;
				wr_req = 1;
				next_write_reg = 0;
				case (busaddr[1:0])
				2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
				2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
				2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
				2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
				endcase
				if(insn[21] /* W */ | !insn[24] /* P */) begin
					if(!rw_wait)
						next_lsr_state = 4'b0100;
				end else if (!rw_wait)
					next_lsr_state = 4'b1000;
			end
			4'b0100: begin
				outstall = 1;
				rd_req = 0;
				wr_req= 0;
				next_outbubble = 0;
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsr_state = 4'b1000;
			end
			4'b1000: begin
				rd_req = 0;
				wr_req= 0;
				outstall = 0;
				next_lsr_state = 4'b0001;
			end
			default: begin end
			endcase
			
			if ((lsr_state == 4'b0001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsr_state = 4'b0001;
			end
		end
		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
		`DECODE_LDMSTM: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			data_size = 3'b100;
			case(lsm_state)
			4'b0001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
				next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                            op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 4'b0010;
			end
			4'b0010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
					next_outcpsrup = 1;
				end

				offset = prev_offset + 6'h4;
				offset_sel = insn[24] ? offset : prev_offset;
				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
				if(insn[20]) begin
					next_write_reg = !rw_wait;
					next_write_num = cur_reg;
					next_write_data = rd_data;
				end
				if (rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;	/* whoops, do this one again */
				end

				st_read = cur_reg;
				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
				busaddr = raddr;
				
				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 4'b0100;
				end
			end
			4'b0100: begin
				outstall = 1;
				next_outbubble = 0;
				next_write_reg = insn[21] /* writeback */;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 4'b1000;
				$display("LDMSTM: Stage 3: Writing back");
			end
			4'b1000: begin
				outstall = 0;
				next_lsm_state = 4'b0001;
			end
			default: $stop;
			endcase
			if ((lsm_state == 4'b0001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsm_state = 4'b0001;
			end
			$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
		end
		`DECODE_LDCSTC: if(!inbubble) begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: if(!inbubble) begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: if(!inbubble) begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = cp_read;
				end else begin
					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
					next_outcpsrup = 1;
				end
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
			end
			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
		end
		default: begin end
		endcase
		
		if ((flush || delayedflush) && !outstall)
			next_outbubble = 1'b1;
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8	6
ab7ee9fc JW	7	input flush,
ab7ee9fc JW	8
b3bb2fb8 CL	9	/* bus interface */
	10	output reg [31:0] busaddr,
	11	output reg rd_req,
	12	output reg wr_req,
	13	input rw_wait,
	14	output reg [31:0] wr_data,
	15	input [31:0] rd_data,
9fc6c23c	16	output reg [2:0] data_size,
b3bb2fb8 CL	17
	18	/* regfile interface */
	19	output reg [3:0] st_read,
	20	input [31:0] st_data,
a02ca509	21
979f2bd7 JW	22	/* Coprocessor interface */
	23	output reg cp_req,
	24	input cp_ack,
	25	input cp_busy,
804dc0bc	26	output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c JW	27	input [31:0] cp_read,
43e4332c JW	28	output reg [31:0] cp_write,
979f2bd7	29
a02ca509 JW	30	/* stage inputs */
	31	input inbubble,
	32	input [31:0] pc,
	33	input [31:0] insn,
e68b2378 JW	34	input [31:0] op0,
e68b2378 JW	35	input [31:0] op1,
6d0f9d82	36	input [31:0] op2,
efd1aa13 CL	37	input [31:0] spsr,
efd1aa13 CL	38	input [31:0] cpsr,
fdecc897	39	input cpsrup,
a02ca509 JW	40	input write_reg,
	41	input [3:0] write_num,
	42	input [31:0] write_data,
b3bb2fb8	43
a02ca509 JW	44	/* outputs */
	45	output reg outstall,
	46	output reg outbubble,
b3bb2fb8	47	output reg [31:0] outpc,
a02ca509 JW	48	output reg [31:0] outinsn,
	49	output reg out_write_reg = 1'b0,
	50	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13	51	output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc	52	output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897 JW	53	output reg [31:0] outcpsr = 32'hxxxxxxxx,
fdecc897 JW	54	output reg outcpsrup = 1'hx
a02ca509	55	);
b3bb2fb8	56
efd1aa13	57	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897	58	reg next_outcpsrup;
666ceb03	59	reg [31:0] prevaddr;
e08b748a	60	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	61	reg next_writeback;
e08b748a	62
804dc0bc JW	63	reg next_outbubble;
	64	reg next_write_reg;
	65	reg [3:0] next_write_num;
	66	reg [31:0] next_write_data;
74d3729c	67
6d18bf27	68	reg [3:0] lsr_state = 4'b0001, next_lsr_state;
666ceb03 CL	69	reg [31:0] align_s1, align_s2, align_rddata;
666ceb03 CL	70
4d7253f1	71	reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03 CL	72	reg [31:0] lsrh_rddata;
	73	reg [15:0] lsrh_rddata_s1;
	74	reg [7:0] lsrh_rddata_s2;
9a0d0e43	75
b783a475	76	reg [15:0] regs, next_regs;
4d7253f1	77	reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f	78	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	79
9a0d0e43 CL	80	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	81	reg [1:0] swp_state = 2'b01, next_swp_state;
6d18bf27 JW	82
	83	reg do_rd_data_latch;
	84	reg [31:0] rd_data_latch = 32'hxxxxxxxx;
a02ca509 JW	85
	86	always @(posedge clk)
	87	begin
	88	outpc <= pc;
	89	outinsn <= insn;
c65110a8 JW	90	outbubble <= next_outbubble;
	91	out_write_reg <= next_write_reg;
	92	out_write_num <= next_write_num;
	93	out_write_data <= next_write_data;
e68b2378	94	regs <= next_regs;
e08b748a	95	prev_reg <= cur_reg;
95704fd3 JW	96	if (!rw_wait)
95704fd3 JW	97	prev_offset <= offset;
b114e03f	98	prev_raddr <= raddr;
ab7ee9fc JW	99	outcpsr <= next_outcpsr;
ab7ee9fc JW	100	outspsr <= spsr;
fdecc897	101	outcpsrup <= next_outcpsrup;
9a0d0e43	102	swp_state <= next_swp_state;
666ceb03 CL	103	lsm_state <= next_lsm_state;
	104	lsr_state <= next_lsr_state;
	105	lsrh_state <= next_lsrh_state;
6d18bf27 JW	106	if (do_rd_data_latch)
6d18bf27 JW	107	rd_data_latch <= rd_data;
666ceb03	108	prevaddr <= addr;
a02ca509	109	end
d73619a2 JW	110
	111	reg delayedflush = 0;
	112	always @(posedge clk)
	113	if (flush && outstall /* halp! I can't do it now, maybe later? */)
	114	delayedflush <= 1;
	115	else if (!outstall /* anything has been handled this time around */)
	116	delayedflush <= 0;
b3bb2fb8 CL	117
	118	always @(*)
	119	begin
666ceb03	120	addr = prevaddr;
b3bb2fb8 CL	121	raddr = 32'hxxxxxxxx;
	122	rd_req = 1'b0;
	123	wr_req = 1'b0;
	124	wr_data = 32'hxxxxxxxx;
	125	busaddr = 32'hxxxxxxxx;
2bcc55d5	126	data_size = 3'bxxx;
b3bb2fb8	127	outstall = 1'b0;
6d18bf27	128	do_rd_data_latch = 0;
a02ca509 JW	129	next_write_reg = write_reg;
	130	next_write_num = write_num;
	131	next_write_data = write_data;
c65110a8	132	next_outbubble = inbubble;
9a0d0e43	133	next_regs = regs;
979f2bd7	134	cp_req = 1'b0;
43e4332c JW	135	cp_rnw = 1'bx;
43e4332c JW	136	cp_write = 32'hxxxxxxxx;
b114e03f	137	offset = prev_offset;
4d7253f1	138	next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
fdecc897	139	next_outcpsrup = cpsrup;
666ceb03	140	lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c CL	141	lsrh_rddata_s1 = 16'hxxxx;
9fc6c23c CL	142	lsrh_rddata_s2 = 8'hxx;
9a0d0e43 CL	143	next_lsm_state = lsm_state;
9a0d0e43 CL	144	next_lsr_state = lsr_state;
666ceb03	145	next_lsrh_state = lsrh_state;
9a0d0e43 CL	146	next_swp_oldval = swp_oldval;
	147	next_swp_state = swp_state;
	148	cur_reg = prev_reg;
9f082c0b	149
5989b2f5	150	/* XXX shit not given about endianness */
d73619a2	151	casez(insn)
5989b2f5 CL	152	`DECODE_ALU_SWP: if(!inbubble) begin
	153	outstall = rw_wait;
	154	next_outbubble = rw_wait;
	155	busaddr = {op0[31:2], 2'b0};
2bcc55d5	156	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 CL	157	case(swp_state)
	158	2'b01: begin
	159	rd_req = 1'b1;
	160	outstall = 1'b1;
	161	if(!rw_wait) begin
	162	next_swp_state = 2'b10;
	163	next_swp_oldval = rd_data;
9a0d0e43	164	end
fb529aac	165	$display("SWP: read stage");
9a0d0e43	166	end
5989b2f5 CL	167	2'b10: begin
5989b2f5 CL	168	wr_req = 1'b1;
2bcc55d5	169	wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5 CL	170	next_write_reg = 1'b1;
5989b2f5 CL	171	next_write_num = insn[15:12];
2bcc55d5	172	next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5 CL	173	if(!rw_wait)
5989b2f5 CL	174	next_swp_state = 2'b01;
fb529aac	175	$display("SWP: write stage");
5989b2f5 CL	176	end
	177	default: begin end
	178	endcase
9a0d0e43	179	end
fb529aac	180	`DECODE_ALU_MULT: begin end
666ceb03 CL	181	`DECODE_ALU_HDATA_REG,
	182	`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
	183	next_outbubble = rw_wait;
	184	outstall = rw_wait;
	185	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	186	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	187	busaddr = raddr;
	188	/* rotate to correct position */
	189	case(insn[6:5])
	190	2'b00: begin end /* swp */
	191	2'b01: begin /* unsigned half */
	192	wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5	193	data_size = 3'b010;
666ceb03 CL	194	lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
	195	end
	196	2'b10: begin /* signed byte */
	197	wr_data = {4{op2[7:0]}};
2bcc55d5	198	data_size = 3'b001;
666ceb03 CL	199	lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
	200	lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
	201	lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
	202	end
	203	2'b11: begin /* signed half */
	204	wr_data = {2{op2[15:0]}};
2bcc55d5	205	data_size = 3'b010;
666ceb03 CL	206	lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
	207	end
	208	endcase
	209
	210	case(lsrh_state)
4d7253f1	211	3'b001: begin
666ceb03 CL	212	rd_req = insn[20];
	213	wr_req = ~insn[20];
	214	next_write_num = insn[15:12];
	215	next_write_data = lsrh_rddata;
	216	if(insn[20]) begin
	217	next_write_reg = 1'b1;
	218	end
d64d6ef9	219	if(insn[21] \| !insn[24]) begin
666ceb03 CL	220	outstall = 1'b1;
666ceb03 CL	221	if(!rw_wait)
4d7253f1	222	next_lsrh_state = 3'b010;
666ceb03	223	end
fb529aac	224	$display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
666ceb03	225	end
4d7253f1 JW	226	3'b010: begin
4d7253f1 JW	227	next_outbubble = 1'b0;
666ceb03 CL	228	next_write_reg = 1'b1;
	229	next_write_num = insn[19:16];
	230	next_write_data = addr;
4d7253f1 JW	231	next_lsrh_state = 3'b100;
	232	end
	233	3'b100: begin
	234	outstall = 0;
	235	next_lsrh_state = 3'b001;
666ceb03 CL	236	end
	237	default: begin end
	238	endcase
d64d6ef9 JW	239
	240	if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
	241	outstall = 1'b0;
	242	next_lsrh_state = 3'b001;
	243	end
666ceb03	244	end
b3bb2fb8	245	`DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 CL	246	`DECODE_LDRSTR: if(!inbubble) begin
	247	next_outbubble = rw_wait;
	248	outstall = rw_wait;
	249	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be	250	raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 CL	251	busaddr = raddr;
666ceb03 CL	252	/* rotate to correct position */
5989b2f5 CL	253	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	254	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	255	/* select byte or word */
	256	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
6d18bf27	257	wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5	258	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5	259	case(lsr_state)
6d18bf27 JW	260	4'b0001: begin
	261	rd_req = insn[20] /* L / \|\| insn[22] / B */;
	262	wr_req = !insn[20] /* L / && !insn[22]/ B */;
fb529aac	263	next_write_reg = insn[20] /* L */;
666ceb03	264	next_write_num = insn[15:12];
fb529aac	265	if(insn[20] /* L */) begin
6d18bf27	266	next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
a02ca509	267	end
6d18bf27 JW	268	if (insn[22] /* B / && !insn[20] / L */) begin
	269	do_rd_data_latch = 1;
	270	outstall = 1'b1;
	271	if (!rw_wait)
	272	next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
	273	end else if(insn[21] /* W / \| !insn[24] / P */) begin
5989b2f5 CL	274	outstall = 1'b1;
5989b2f5 CL	275	if(!rw_wait)
6d18bf27	276	next_lsr_state = 4'b0100;
a02ca509	277	end
d73619a2	278	$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8	279	end
6d18bf27 JW	280	4'b0010: begin
6d18bf27 JW	281	$display("LDRSTR: Handling STRB");
4d7253f1	282	outstall = 1;
6d18bf27 JW	283	rd_req = 0;
	284	wr_req = 1;
	285	next_write_reg = 0;
	286	case (busaddr[1:0])
	287	2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
	288	2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
	289	2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
	290	2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
	291	endcase
	292	if(insn[21] /* W / \| !insn[24] / P */) begin
	293	if(!rw_wait)
	294	next_lsr_state = 4'b0100;
	295	end else if (!rw_wait)
	296	next_lsr_state = 4'b1000;
	297	end
	298	4'b0100: begin
	299	outstall = 1;
	300	rd_req = 0;
	301	wr_req= 0;
4d7253f1	302	next_outbubble = 0;
5989b2f5 CL	303	next_write_reg = 1'b1;
	304	next_write_num = insn[19:16];
	305	next_write_data = addr;
6d18bf27	306	next_lsr_state = 4'b1000;
4d7253f1	307	end
6d18bf27 JW	308	4'b1000: begin
	309	rd_req = 0;
	310	wr_req= 0;
4d7253f1	311	outstall = 0;
6d18bf27	312	next_lsr_state = 4'b0001;
5989b2f5 CL	313	end
	314	default: begin end
	315	endcase
d64d6ef9	316
6d18bf27	317	if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
d64d6ef9	318	outstall = 1'b0;
6d18bf27	319	next_lsr_state = 4'b0001;
d64d6ef9	320	end
b3bb2fb8	321	end
5989b2f5 CL	322	/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
5989b2f5 CL	323	`DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 CL	324	outstall = rw_wait;
9a0d0e43 CL	325	next_outbubble = rw_wait;
2bcc55d5	326	data_size = 3'b100;
9a0d0e43	327	case(lsm_state)
4d7253f1	328	4'b0001: begin
b114e03f CL	329	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
b114e03f CL	330	/** verilator can suck my dick */
b957d34d JW	331	$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
	332	next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	333	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f	334	offset = 6'b0;
d64d6ef9 JW	335	outstall = 1'b1;
d64d6ef9 JW	336	next_lsm_state = 4'b0010;
e08b748a	337	end
4d7253f1	338	4'b0010: begin
9a0d0e43 CL	339	rd_req = insn[20];
9a0d0e43 CL	340	wr_req = ~insn[20];
9f082c0b CL	341	casez(regs)
9f082c0b CL	342	16'b???????????????1: begin
e08b748a	343	cur_reg = 4'h0;
b114e03f	344	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	345	end
9f082c0b CL	346	16'b??????????????10: begin
e08b748a	347	cur_reg = 4'h1;
b114e03f	348	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	349	end
9f082c0b CL	350	16'b?????????????100: begin
e08b748a	351	cur_reg = 4'h2;
b114e03f	352	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	353	end
9f082c0b CL	354	16'b????????????1000: begin
e08b748a	355	cur_reg = 4'h3;
b114e03f	356	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	357	end
9f082c0b CL	358	16'b???????????10000: begin
e08b748a	359	cur_reg = 4'h4;
b114e03f	360	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	361	end
9f082c0b CL	362	16'b??????????100000: begin
e08b748a	363	cur_reg = 4'h5;
b114e03f	364	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	365	end
9f082c0b CL	366	16'b?????????1000000: begin
e08b748a	367	cur_reg = 4'h6;
b114e03f	368	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	369	end
9f082c0b CL	370	16'b????????10000000: begin
e08b748a	371	cur_reg = 4'h7;
b114e03f	372	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	373	end
9f082c0b CL	374	16'b???????100000000: begin
e08b748a	375	cur_reg = 4'h8;
b114e03f	376	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	377	end
9f082c0b CL	378	16'b??????1000000000: begin
e08b748a	379	cur_reg = 4'h9;
b114e03f	380	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	381	end
9f082c0b CL	382	16'b?????10000000000: begin
e08b748a	383	cur_reg = 4'hA;
b114e03f	384	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	385	end
9f082c0b CL	386	16'b????100000000000: begin
e08b748a	387	cur_reg = 4'hB;
b114e03f	388	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	389	end
9f082c0b CL	390	16'b???1000000000000: begin
e08b748a	391	cur_reg = 4'hC;
b114e03f	392	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	393	end
9f082c0b CL	394	16'b??10000000000000: begin
e08b748a	395	cur_reg = 4'hD;
b114e03f	396	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	397	end
9f082c0b CL	398	16'b?100000000000000: begin
e08b748a	399	cur_reg = 4'hE;
b114e03f	400	next_regs = {regs[15], 15'b0};
9f082c0b CL	401	end
9f082c0b CL	402	16'b1000000000000000: begin
e08b748a	403	cur_reg = 4'hF;
9f082c0b CL	404	next_regs = 16'b0;
	405	end
	406	default: begin
e08b748a CL	407	cur_reg = 4'hx;
e08b748a CL	408	next_regs = 16'b0;
9f082c0b CL	409	end
9f082c0b CL	410	endcase
b957d34d	411	cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13 CL	412	if(cur_reg == 4'hF && insn[22]) begin
efd1aa13 CL	413	next_outcpsr = spsr;
fdecc897	414	next_outcpsrup = 1;
efd1aa13	415	end
b114e03f	416
95704fd3	417	offset = prev_offset + 6'h4;
d73619a2 JW	418	offset_sel = insn[24] ? offset : prev_offset;
	419	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	420	if(insn[20]) begin
	421	next_write_reg = !rw_wait;
	422	next_write_num = cur_reg;
	423	next_write_data = rd_data;
	424	end
	425	if (rw_wait) begin
	426	next_regs = regs;
	427	cur_reg = prev_reg; /* whoops, do this one again */
b114e03f CL	428	end
	429
	430	st_read = cur_reg;
b957d34d	431	wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03	432	busaddr = raddr;
b957d34d	433
d73619a2	434	$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43 CL	435
	436	outstall = 1'b1;
	437
	438	if(next_regs == 16'b0) begin
4d7253f1	439	next_lsm_state = 4'b0100;
9a0d0e43 CL	440	end
9a0d0e43 CL	441	end
4d7253f1 JW	442	4'b0100: begin
	443	outstall = 1;
	444	next_outbubble = 0;
b957d34d	445	next_write_reg = insn[21] /* writeback */;
9a0d0e43 CL	446	next_write_num = insn[19:16];
9a0d0e43 CL	447	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
4d7253f1	448	next_lsm_state = 4'b1000;
d73619a2	449	$display("LDMSTM: Stage 3: Writing back");
b783a475	450	end
4d7253f1 JW	451	4'b1000: begin
	452	outstall = 0;
	453	next_lsm_state = 4'b0001;
	454	end
d73619a2	455	default: $stop;
9a0d0e43	456	endcase
d64d6ef9 JW	457	if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
	458	outstall = 1'b0;
	459	next_lsm_state = 4'b0001;
	460	end
d73619a2	461	$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8	462	end
5989b2f5	463	`DECODE_LDCSTC: if(!inbubble) begin
43e4332c JW	464	$display("WARNING: Unimplemented LDCSTC");
43e4332c JW	465	end
5989b2f5	466	`DECODE_CDP: if(!inbubble) begin
43e4332c JW	467	cp_req = 1;
	468	if (cp_busy) begin
	469	outstall = 1;
	470	next_outbubble = 1;
	471	end
	472	if (!cp_ack) begin
	473	/* XXX undefined instruction trap */
	474	$display("WARNING: Possible CDP undefined instruction");
	475	end
	476	end
5989b2f5	477	`DECODE_MRCMCR: if(!inbubble) begin
43e4332c JW	478	cp_req = 1;
	479	cp_rnw = insn[20] /* L */;
	480	if (insn[20] == 0 /* store to coprocessor */)
	481	cp_write = op0;
	482	else begin
d1d0eb8e JW	483	if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
	484	next_write_reg = 1'b1;
	485	next_write_num = insn[15:12];
	486	next_write_data = cp_read;
fdecc897	487	end else begin
d1d0eb8e	488	next_outcpsr = {cp_read[31:28], cpsr[27:0]};
fdecc897 JW	489	next_outcpsrup = 1;
fdecc897 JW	490	end
43e4332c JW	491	end
	492	if (cp_busy) begin
	493	outstall = 1;
	494	next_outbubble = 1;
	495	end
	496	if (!cp_ack) begin
838e283e	497	$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c	498	end
838e283e	499	$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c	500	end
b3bb2fb8 CL	501	default: begin end
b3bb2fb8 CL	502	endcase
d73619a2 JW	503
	504	if ((flush \|\| delayedflush) && !outstall)
	505	next_outbubble = 1'b1;
b3bb2fb8	506	end
b3bb2fb8	507	endmodule