Add a BigBlockRAM that's 8MB (and obviously not very synthesizable). Make system...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 05:56:31 +0000 (00:56 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 05:56:31 +0000 (00:56 -0500)
BigBlockRAM.v [new file with mode: 0644]
system.v

diff --git a/BigBlockRAM.v b/BigBlockRAM.v
new file mode 100644 (file)
index 0000000..b8ccbff
--- /dev/null
@@ -0,0 +1,41 @@
+module BigBlockRAM(
+       input clk,
+       input [31:0] bus_addr,
+       output wire [31:0] bus_rdata,
+       input [31:0] bus_wdata,
+       input bus_rd,
+       input bus_wr,
+       output wire bus_ready
+       );
+       
+       /* This module is mapped in physical memory from 0x00000000 to
+        * 0x00800000.  rdata and ready must be driven to zero if the
+        * address is not within the range of this module.
+        */
+       wire decode = bus_addr[31:23] == 9'b0;
+       wire [22:0] ramaddr = {bus_addr[22:2], 2'b0};   /* mask off lower two bits
+                                                        * for word alignment */
+
+       reg [31:0] data [((8*1024*1024) / 4 - 1):0];
+       
+       reg [31:0] temprdata = 0;
+       reg [22:0] lastread = 23'h7FFFFFFF;
+       assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
+       
+       assign bus_ready = decode &&
+               (bus_wr || (bus_rd && (lastread == ramaddr)));
+       
+       initial
+               $readmemh("ram.hex", data);
+       
+       always @(posedge clk)
+       begin
+               if (bus_wr && decode)
+                       data[ramaddr[22:2]] = bus_wdata;
+               
+               /* This is not allowed to be conditional -- stupid Xilinx
+                * blockram. */
+               temprdata <= data[ramaddr[22:2]];
+               lastread <= ramaddr;
+       end
+endmodule
index 1741203..07adfd8 100644 (file)
--- a/system.v
+++ b/system.v
@@ -127,7 +127,12 @@ module System(input clk);
                .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
                .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
 
-       BlockRAM blockram(
+`ifdef verilator
+       BigBlockRAM
+`else
+       BlockRAM
+`endif
+       blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
                .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
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