[firearm.git] / system.v

`define BUS_ICACHE 1
`define BUS_DCACHE 0

module System(input clk, input rst
`ifdef verilator
`else
	, output wire [8:0] sys_odata,
	input [8:0] sys_idata,
	output wire sys_tookdata
`endif
	);
	
	wire [7:0] bus_req;
	wire [7:0] bus_ack;
	wire [31:0] bus_addr;
	wire [31:0] bus_rdata;
	wire [31:0] bus_wdata;
	wire bus_rd, bus_wr;
	wire bus_ready;

	wire bus_req_icache;
	wire bus_req_dcache;
	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
	
	wire [31:0] bus_addr_icache;
	wire [31:0] bus_wdata_icache;
	wire bus_rd_icache;
	wire bus_wr_icache;
	
	wire [31:0] bus_addr_dcache;
	wire [31:0] bus_wdata_dcache;
	wire bus_rd_dcache;
	wire bus_wr_dcache;
	
	wire [31:0] bus_rdata_blockram;
	wire bus_ready_blockram;
	
	assign bus_addr = bus_addr_icache | bus_addr_dcache;
	assign bus_rdata = bus_rdata_blockram;
	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
	assign bus_rd = bus_rd_icache | bus_rd_dcache;
	assign bus_wr = bus_wr_icache | bus_wr_dcache;
	assign bus_ready = bus_ready_blockram;

	wire [31:0] icache_rd_addr;
	wire icache_rd_req;
	wire icache_rd_wait;
	wire [31:0] icache_rd_data;
	
	wire [31:0] dcache_addr;
	wire dcache_rd_req, dcache_wr_req;
	wire dcache_rw_wait;
	wire [31:0] dcache_wr_data, dcache_rd_data;
	
	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
	wire decode_out_carry;
	
	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	wire regfile_write;
	wire [3:0] regfile_write_reg;
	wire [31:0] regfile_write_data;
	
	wire execute_out_write_reg;
	wire [3:0] execute_out_write_num;
	wire [31:0] execute_out_write_data;
	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
	wire [31:0] execute_out_cpsr, execute_out_spsr;
	wire execute_out_cpsrup;
	
	wire jmp_out_execute, jmp_out_writeback;
	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	wire jmp = jmp_out_execute | jmp_out_writeback;
	wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
	
	wire memory_out_write_reg;
	wire [3:0] memory_out_write_num;
	wire [31:0] memory_out_write_data;
	wire [31:0] memory_out_cpsr, memory_out_spsr;
	wire memory_out_cpsrup;
	
	wire [31:0] writeback_out_cpsr, writeback_out_spsr;

	wire cp_ack_terminal;
	wire cp_busy_terminal;
	wire [31:0] cp_read_terminal;
	
	wire cp_req;
	wire [31:0] cp_insn;
	wire cp_ack = cp_ack_terminal;
	wire cp_busy = cp_busy_terminal;
	wire cp_rnw;
	wire [31:0] cp_read = cp_read_terminal;
	wire [31:0] cp_write;
	
	wire stall_cause_issue;
	wire stall_cause_execute;
	wire stall_cause_memory;
	wire bubble_out_fetch;
	wire bubble_out_issue;
	wire bubble_out_execute;
	wire bubble_out_memory;
	wire [31:0] insn_out_fetch;
	wire [31:0] insn_out_issue;
	wire [31:0] insn_out_execute;
	wire [31:0] insn_out_memory;
	wire [31:0] pc_out_fetch;
	wire [31:0] pc_out_issue;
	wire [31:0] pc_out_execute;
	wire [31:0] pc_out_memory;
	
	wire Nrst = ~rst;
	
	/*AUTOWIRE*/
	// Beginning of automatic wires (for undeclared instantiated-module outputs)
	wire		bubble_1a;		// From fetch of Fetch.v
	wire [31:0]	ic__rd_addr_0a;		// From fetch of Fetch.v
	wire [31:0]	ic__rd_data_1a;		// From icache of ICache.v
	wire		ic__rd_req_0a;		// From fetch of Fetch.v
	wire		ic__rd_wait_0a;		// From icache of ICache.v
	wire [31:0]	insn_1a;		// From fetch of Fetch.v
	wire [31:0]	pc_1a;			// From fetch of Fetch.v
	wire [31:0]	rf__rdata_0_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_1_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_2_1a;		// From regfile of RegFile.v
	wire [31:0]	rf__rdata_3_4a;		// From regfile of RegFile.v
	wire [3:0]	rf__read_0_1a;		// From decode of Decode.v
	wire [3:0]	rf__read_1_1a;		// From decode of Decode.v
	wire [3:0]	rf__read_2_1a;		// From decode of Decode.v
	wire		stall_0a;		// From issue of Issue.v
	// End of automatics

	wire execute_out_backflush;
	wire writeback_out_backflush;

	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));

	/* XXX reset? */
	/* ICache AUTO_TEMPLATE (
		.clk(clk),
		.bus_req(bus_req_icache),
		.bus_ack(bus_ack_icache),
		.bus_addr(bus_addr_icache),
		.bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_icache),
		.bus_rd(bus_rd_icache),
		.bus_wr(bus_wr_icache),
		.bus_ready(bus_ready),
		); */
	ICache icache(/*AUTOINST*/
		      // Outputs
		      .ic__rd_wait_0a	(ic__rd_wait_0a),
		      .ic__rd_data_1a	(ic__rd_data_1a[31:0]),
		      .bus_req		(bus_req_icache),	 // Templated
		      .bus_addr		(bus_addr_icache),	 // Templated
		      .bus_wdata	(bus_wdata_icache),	 // Templated
		      .bus_rd		(bus_rd_icache),	 // Templated
		      .bus_wr		(bus_wr_icache),	 // Templated
		      // Inputs
		      .clk		(clk),			 // Templated
		      .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		      .ic__rd_req_0a	(ic__rd_req_0a),
		      .bus_ack		(bus_ack_icache),	 // Templated
		      .bus_rdata	(bus_rdata),		 // Templated
		      .bus_ready	(bus_ready));		 // Templated
	
	DCache dcache(
		.clk(clk),
		.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
		.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));

`ifdef verilator
	BigBlockRAM
`else
	BlockRAM
`endif
	blockram(
		.clk(clk),
		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
		.bus_ready(bus_ready_blockram));

	/* Fetch AUTO_TEMPLATE (
		.stall_0a(stall_cause_issue),
		.jmp_0a(jmp),
		.jmppc_0a(jmppc),
		);
	*/
	Fetch fetch(
		/*AUTOINST*/
		    // Outputs
		    .ic__rd_addr_0a	(ic__rd_addr_0a[31:0]),
		    .ic__rd_req_0a	(ic__rd_req_0a),
		    .bubble_1a		(bubble_1a),
		    .insn_1a		(insn_1a[31:0]),
		    .pc_1a		(pc_1a[31:0]),
		    // Inputs
		    .clk		(clk),
		    .Nrst		(Nrst),
		    .ic__rd_wait_0a	(ic__rd_wait_0a),
		    .ic__rd_data_1a	(ic__rd_data_1a[31:0]),
		    .stall_0a		(stall_cause_issue),	 // Templated
		    .jmp_0a		(jmp),			 // Templated
		    .jmppc_0a		(jmppc));		 // Templated
	
	/* Issue AUTO_TEMPLATE (
		.stall_1a(stall_cause_execute),
		.flush(execute_out_backflush | writeback_out_backflush),
		.cpsr_1a(writeback_out_cpsr),
		.bubble_2a(bubble_out_issue),
		.pc_2a(pc_out_issue),
		.insn_2a(insn_out_issue),
		);
	*/
	Issue issue(
		/*AUTOINST*/
		    // Outputs
		    .stall_0a		(stall_0a),
		    .bubble_2a		(bubble_out_issue),	 // Templated
		    .pc_2a		(pc_out_issue),		 // Templated
		    .insn_2a		(insn_out_issue),	 // Templated
		    // Inputs
		    .clk		(clk),
		    .Nrst		(Nrst),
		    .stall_1a		(stall_cause_execute),	 // Templated
		    .flush		(execute_out_backflush | writeback_out_backflush), // Templated
		    .bubble_1a		(bubble_1a),
		    .insn_1a		(insn_1a[31:0]),
		    .pc_1a		(pc_1a[31:0]),
		    .cpsr_1a		(writeback_out_cpsr));	 // Templated
	
	/* RegFile AUTO_TEMPLATE (
		.spsr(regfile_spsr),
		.write(regfile_write),
		.write_reg(regfile_write_reg),
		.write_data(regfile_write_data),
		);
	*/
	wire [3:0] rf__read_3_4a;
	RegFile regfile(
		/*AUTOINST*/
			// Outputs
			.rf__rdata_0_1a	(rf__rdata_0_1a[31:0]),
			.rf__rdata_1_1a	(rf__rdata_1_1a[31:0]),
			.rf__rdata_2_1a	(rf__rdata_2_1a[31:0]),
			.rf__rdata_3_4a	(rf__rdata_3_4a[31:0]),
			.spsr		(regfile_spsr),		 // Templated
			// Inputs
			.clk		(clk),
			.Nrst		(Nrst),
			.rf__read_0_1a	(rf__read_0_1a[3:0]),
			.rf__read_1_1a	(rf__read_1_1a[3:0]),
			.rf__read_2_1a	(rf__read_2_1a[3:0]),
			.rf__read_3_4a	(rf__read_3_4a[3:0]),
			.write		(regfile_write),	 // Templated
			.write_reg	(regfile_write_reg),	 // Templated
			.write_data	(regfile_write_data));	 // Templated
	
	/* Decode AUTO_TEMPLATE (
		.stall(stall_cause_execute),
		.incpsr(writeback_out_cpsr),
		.inspsr(writeback_out_spsr),
		.op0(decode_out_op0),
		.op1(decode_out_op1),
		.op2(decode_out_op2),
		.carry(decode_out_carry),
		.outcpsr(decode_out_cpsr),
		.outspsr(decode_out_spsr),
		);
	*/
	Decode decode(
		/*AUTOINST*/
		      // Outputs
		      .op0		(decode_out_op0),	 // Templated
		      .op1		(decode_out_op1),	 // Templated
		      .op2		(decode_out_op2),	 // Templated
		      .carry		(decode_out_carry),	 // Templated
		      .outcpsr		(decode_out_cpsr),	 // Templated
		      .outspsr		(decode_out_spsr),	 // Templated
		      .rf__read_0_1a	(rf__read_0_1a[3:0]),
		      .rf__read_1_1a	(rf__read_1_1a[3:0]),
		      .rf__read_2_1a	(rf__read_2_1a[3:0]),
		      // Inputs
		      .clk		(clk),
		      .stall		(stall_cause_execute),	 // Templated
		      .insn_1a		(insn_1a[31:0]),
		      .pc_1a		(pc_1a[31:0]),
		      .incpsr		(writeback_out_cpsr),	 // Templated
		      .inspsr		(writeback_out_spsr),	 // Templated
		      .rf__rdata_0_1a	(rf__rdata_0_1a[31:0]),
		      .rf__rdata_1_1a	(rf__rdata_1_1a[31:0]),
		      .rf__rdata_2_1a	(rf__rdata_2_1a[31:0]));
	
	Execute execute(
		.clk(clk), .Nrst(~rst),
		.stall(stall_cause_memory), .flush(writeback_out_backflush),
		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
		.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
		.op2(decode_out_op2), .carry(decode_out_carry),
		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
		.write_data(execute_out_write_data),
		.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
		.outpc(pc_out_execute), .outinsn(insn_out_execute),
		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
		.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
	assign execute_out_backflush = jmp;
	
	assign cp_insn = insn_out_execute;
	Memory memory(
		.clk(clk), .Nrst(~rst),
		/* stall? */ .flush(writeback_out_backflush),
		.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),
		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
		.spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
		.outpc(pc_out_memory), .outinsn(insn_out_memory),
		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
		.out_write_data(memory_out_write_data),
		.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
		.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
	
	Terminal terminal(	
		.clk(clk),
		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
		.cp_read(cp_read_terminal), .cp_write(cp_write)
`ifdef verilator
`else
		, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
`endif
		);
	
	Writeback writeback(
		.clk(clk),
		.inbubble(bubble_out_memory),
		.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
		.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
		.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
		.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	assign writeback_out_backflush = jmp_out_writeback;

	reg [31:0] clockno = 0;
	always @(posedge clk)
	begin
		clockno <= clockno + 1;
		$display("------------------------------------------------------------------------------");
		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
	end
endmodule
Commit	Line	Data
e3a9107a JW	1	`define BUS_ICACHE 1
e3a9107a JW	2	`define BUS_DCACHE 0
ee406839	3
a4f724e6	4	module System(input clk, input rst
fd003c7a JW	5	`ifdef verilator
	6	`else
	7	, output wire [8:0] sys_odata,
	8	input [8:0] sys_idata,
	9	output wire sys_tookdata
	10	`endif
	11	);
	12
ee406839 JW	13	wire [7:0] bus_req;
	14	wire [7:0] bus_ack;
	15	wire [31:0] bus_addr;
a0bb35e7 JW	16	wire [31:0] bus_rdata;
a0bb35e7 JW	17	wire [31:0] bus_wdata;
ee406839 JW	18	wire bus_rd, bus_wr;
ee406839 JW	19	wire bus_ready;
45fa96c0	20
03f45381 JW	21	wire bus_req_icache;
03f45381 JW	22	wire bus_req_dcache;
e3a9107a	23	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839	24	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381	25	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0	26
ee406839 JW	27	wire [31:0] bus_addr_icache;
	28	wire [31:0] bus_wdata_icache;
	29	wire bus_rd_icache;
	30	wire bus_wr_icache;
	31
03f45381 JW	32	wire [31:0] bus_addr_dcache;
	33	wire [31:0] bus_wdata_dcache;
	34	wire bus_rd_dcache;
	35	wire bus_wr_dcache;
	36
a0bb35e7 JW	37	wire [31:0] bus_rdata_blockram;
	38	wire bus_ready_blockram;
	39
03f45381	40	assign bus_addr = bus_addr_icache \| bus_addr_dcache;
a0bb35e7	41	assign bus_rdata = bus_rdata_blockram;
03f45381 JW	42	assign bus_wdata = bus_wdata_icache \| bus_wdata_dcache;
	43	assign bus_rd = bus_rd_icache \| bus_rd_dcache;
	44	assign bus_wr = bus_wr_icache \| bus_wr_dcache;
a0bb35e7	45	assign bus_ready = bus_ready_blockram;
149bcd1a	46
5d9760a4 JW	47	wire [31:0] icache_rd_addr;
	48	wire icache_rd_req;
	49	wire icache_rd_wait;
	50	wire [31:0] icache_rd_data;
09e28f01	51
03f45381 JW	52	wire [31:0] dcache_addr;
	53	wire dcache_rd_req, dcache_wr_req;
	54	wire dcache_rw_wait;
	55	wire [31:0] dcache_wr_data, dcache_rd_data;
	56
ab7ee9fc	57	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610	58	wire decode_out_carry;
c65110a8 JW	59
	60	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	61	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
ab7ee9fc JW	62	wire regfile_write;
	63	wire [3:0] regfile_write_reg;
	64	wire [31:0] regfile_write_data;
c65110a8	65
bc572c5f JW	66	wire execute_out_write_reg;
	67	wire [3:0] execute_out_write_num;
	68	wire [31:0] execute_out_write_data;
c65110a8	69	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1	70	wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897	71	wire execute_out_cpsrup;
ab7ee9fc JW	72
	73	wire jmp_out_execute, jmp_out_writeback;
	74	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	75	wire jmp = jmp_out_execute \| jmp_out_writeback;
	76	wire [31:0] jmppc = jmppc_out_execute \| jmppc_out_writeback;
5ca27949	77
c65110a8 JW	78	wire memory_out_write_reg;
	79	wire [3:0] memory_out_write_num;
	80	wire [31:0] memory_out_write_data;
ab7ee9fc	81	wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897	82	wire memory_out_cpsrup;
ab7ee9fc JW	83
ab7ee9fc JW	84	wire [31:0] writeback_out_cpsr, writeback_out_spsr;
1d97a095 JW	85
	86	wire cp_ack_terminal;
	87	wire cp_busy_terminal;
	88	wire [31:0] cp_read_terminal;
c65110a8	89
43e4332c	90	wire cp_req;
1d97a095 JW	91	wire [31:0] cp_insn;
	92	wire cp_ack = cp_ack_terminal;
	93	wire cp_busy = cp_busy_terminal;
43e4332c	94	wire cp_rnw;
1d97a095	95	wire [31:0] cp_read = cp_read_terminal;
43e4332c JW	96	wire [31:0] cp_write;
43e4332c JW	97
c65110a8 JW	98	wire stall_cause_issue;
	99	wire stall_cause_execute;
	100	wire stall_cause_memory;
09e28f01 JW	101	wire bubble_out_fetch;
09e28f01 JW	102	wire bubble_out_issue;
2393422a	103	wire bubble_out_execute;
c65110a8	104	wire bubble_out_memory;
09e28f01 JW	105	wire [31:0] insn_out_fetch;
09e28f01 JW	106	wire [31:0] insn_out_issue;
2393422a	107	wire [31:0] insn_out_execute;
c65110a8	108	wire [31:0] insn_out_memory;
09e28f01 JW	109	wire [31:0] pc_out_fetch;
09e28f01 JW	110	wire [31:0] pc_out_issue;
2393422a	111	wire [31:0] pc_out_execute;
c65110a8	112	wire [31:0] pc_out_memory;
2bf779cf	113
a7297aa5 JW	114	wire Nrst = ~rst;
a7297aa5 JW	115
2bf779cf JW	116	/AUTOWIRE/
2bf779cf JW	117	// Beginning of automatic wires (for undeclared instantiated-module outputs)
a7297aa5	118	wire bubble_1a; // From fetch of Fetch.v
2bf779cf	119	wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
3c947a99	120	wire [31:0] ic__rd_data_1a; // From icache of ICache.v
2bf779cf JW	121	wire ic__rd_req_0a; // From fetch of Fetch.v
2bf779cf JW	122	wire ic__rd_wait_0a; // From icache of ICache.v
a7297aa5 JW	123	wire [31:0] insn_1a; // From fetch of Fetch.v
	124	wire [31:0] pc_1a; // From fetch of Fetch.v
	125	wire [31:0] rf__rdata_0_1a; // From regfile of RegFile.v
	126	wire [31:0] rf__rdata_1_1a; // From regfile of RegFile.v
	127	wire [31:0] rf__rdata_2_1a; // From regfile of RegFile.v
	128	wire [31:0] rf__rdata_3_4a; // From regfile of RegFile.v
	129	wire [3:0] rf__read_0_1a; // From decode of Decode.v
	130	wire [3:0] rf__read_1_1a; // From decode of Decode.v
	131	wire [3:0] rf__read_2_1a; // From decode of Decode.v
ae457ae9	132	wire stall_0a; // From issue of Issue.v
2bf779cf	133	// End of automatics
149bcd1a	134
7947b9c7	135	wire execute_out_backflush;
ab7ee9fc	136	wire writeback_out_backflush;
c2b9d4b7	137
ee406839	138	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7	139
2bf779cf JW	140	/* XXX reset? */
2bf779cf JW	141	/* ICache AUTO_TEMPLATE (
a0bb35e7	142	.clk(clk),
2bf779cf JW	143	.bus_req(bus_req_icache),
	144	.bus_ack(bus_ack_icache),
	145	.bus_addr(bus_addr_icache),
	146	.bus_rdata(bus_rdata),
	147	.bus_wdata(bus_wdata_icache),
	148	.bus_rd(bus_rd_icache),
	149	.bus_wr(bus_wr_icache),
	150	.bus_ready(bus_ready),
	151	); */
	152	ICache icache(/AUTOINST/
	153	// Outputs
	154	.ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99	155	.ic__rd_data_1a (ic__rd_data_1a[31:0]),
2bf779cf JW	156	.bus_req (bus_req_icache), // Templated
	157	.bus_addr (bus_addr_icache), // Templated
	158	.bus_wdata (bus_wdata_icache), // Templated
	159	.bus_rd (bus_rd_icache), // Templated
	160	.bus_wr (bus_wr_icache), // Templated
	161	// Inputs
	162	.clk (clk), // Templated
	163	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	164	.ic__rd_req_0a (ic__rd_req_0a),
	165	.bus_ack (bus_ack_icache), // Templated
	166	.bus_rdata (bus_rdata), // Templated
	167	.bus_ready (bus_ready)); // Templated
45fa96c0	168
03f45381 JW	169	DCache dcache(
	170	.clk(clk),
	171	.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
	172	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
	173	.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
	174	.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
	175	.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
	176	.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
	177
90bdd4a8 JW	178	`ifdef verilator
	179	BigBlockRAM
	180	`else
	181	BlockRAM
	182	`endif
	183	blockram(
a0bb35e7 JW	184	.clk(clk),
	185	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	186	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	187	.bus_ready(bus_ready_blockram));
	188
2bf779cf	189	/* Fetch AUTO_TEMPLATE (
2bf779cf JW	190	.stall_0a(stall_cause_issue),
	191	.jmp_0a(jmp),
	192	.jmppc_0a(jmppc),
2bf779cf JW	193	);
	194	*/
	195	Fetch fetch(
	196	/AUTOINST/
	197	// Outputs
	198	.ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
	199	.ic__rd_req_0a (ic__rd_req_0a),
a7297aa5 JW	200	.bubble_1a (bubble_1a),
	201	.insn_1a (insn_1a[31:0]),
	202	.pc_1a (pc_1a[31:0]),
2bf779cf	203	// Inputs
a7297aa5 JW	204	.clk (clk),
a7297aa5 JW	205	.Nrst (Nrst),
2bf779cf	206	.ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99	207	.ic__rd_data_1a (ic__rd_data_1a[31:0]),
2bf779cf JW	208	.stall_0a (stall_cause_issue), // Templated
	209	.jmp_0a (jmp), // Templated
	210	.jmppc_0a (jmppc)); // Templated
09e28f01	211
a7297aa5	212	/* Issue AUTO_TEMPLATE (
ae457ae9	213	.stall_1a(stall_cause_execute),
a7297aa5	214	.flush(execute_out_backflush \| writeback_out_backflush),
ae457ae9 JW	215	.cpsr_1a(writeback_out_cpsr),
	216	.bubble_2a(bubble_out_issue),
	217	.pc_2a(pc_out_issue),
	218	.insn_2a(insn_out_issue),
a7297aa5 JW	219	);
a7297aa5 JW	220	*/
09e28f01	221	Issue issue(
a7297aa5 JW	222	/AUTOINST/
a7297aa5 JW	223	// Outputs
ae457ae9 JW	224	.stall_0a (stall_0a),
	225	.bubble_2a (bubble_out_issue), // Templated
	226	.pc_2a (pc_out_issue), // Templated
	227	.insn_2a (insn_out_issue), // Templated
a7297aa5 JW	228	// Inputs
	229	.clk (clk),
	230	.Nrst (Nrst),
ae457ae9	231	.stall_1a (stall_cause_execute), // Templated
a7297aa5 JW	232	.flush (execute_out_backflush \| writeback_out_backflush), // Templated
	233	.bubble_1a (bubble_1a),
	234	.insn_1a (insn_1a[31:0]),
	235	.pc_1a (pc_1a[31:0]),
ae457ae9	236	.cpsr_1a (writeback_out_cpsr)); // Templated
90ff449a	237
a7297aa5	238	/* RegFile AUTO_TEMPLATE (
ab7ee9fc	239	.spsr(regfile_spsr),
a7297aa5 JW	240	.write(regfile_write),
	241	.write_reg(regfile_write_reg),
	242	.write_data(regfile_write_data),
	243	);
	244	*/
	245	wire [3:0] rf__read_3_4a;
	246	RegFile regfile(
	247	/AUTOINST/
	248	// Outputs
	249	.rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
	250	.rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
	251	.rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
	252	.rf__rdata_3_4a (rf__rdata_3_4a[31:0]),
	253	.spsr (regfile_spsr), // Templated
	254	// Inputs
	255	.clk (clk),
	256	.Nrst (Nrst),
	257	.rf__read_0_1a (rf__read_0_1a[3:0]),
	258	.rf__read_1_1a (rf__read_1_1a[3:0]),
	259	.rf__read_2_1a (rf__read_2_1a[3:0]),
	260	.rf__read_3_4a (rf__read_3_4a[3:0]),
	261	.write (regfile_write), // Templated
	262	.write_reg (regfile_write_reg), // Templated
	263	.write_data (regfile_write_data)); // Templated
5ca27949	264
a7297aa5	265	/* Decode AUTO_TEMPLATE (
e74c7936	266	.stall(stall_cause_execute),
a7297aa5 JW	267	.incpsr(writeback_out_cpsr),
	268	.inspsr(writeback_out_spsr),
	269	.op0(decode_out_op0),
	270	.op1(decode_out_op1),
	271	.op2(decode_out_op2),
	272	.carry(decode_out_carry),
	273	.outcpsr(decode_out_cpsr),
	274	.outspsr(decode_out_spsr),
	275	);
	276	*/
	277	Decode decode(
	278	/AUTOINST/
	279	// Outputs
	280	.op0 (decode_out_op0), // Templated
	281	.op1 (decode_out_op1), // Templated
	282	.op2 (decode_out_op2), // Templated
	283	.carry (decode_out_carry), // Templated
	284	.outcpsr (decode_out_cpsr), // Templated
	285	.outspsr (decode_out_spsr), // Templated
	286	.rf__read_0_1a (rf__read_0_1a[3:0]),
	287	.rf__read_1_1a (rf__read_1_1a[3:0]),
	288	.rf__read_2_1a (rf__read_2_1a[3:0]),
	289	// Inputs
	290	.clk (clk),
	291	.stall (stall_cause_execute), // Templated
	292	.insn_1a (insn_1a[31:0]),
	293	.pc_1a (pc_1a[31:0]),
	294	.incpsr (writeback_out_cpsr), // Templated
	295	.inspsr (writeback_out_spsr), // Templated
	296	.rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
	297	.rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
	298	.rf__rdata_2_1a (rf__rdata_2_1a[31:0]));
5ca27949	299
bc572c5f	300	Execute execute(
a4f724e6	301	.clk(clk), .Nrst(~rst),
ab7ee9fc	302	.stall(stall_cause_memory), .flush(writeback_out_backflush),
bc572c5f	303	.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
ab7ee9fc	304	.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
bc572c5f	305	.op2(decode_out_op2), .carry(decode_out_carry),
2393422a	306	.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
bc572c5f	307	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
149bcd1a	308	.write_data(execute_out_write_data),
ab7ee9fc	309	.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
c65110a8	310	.outpc(pc_out_execute), .outinsn(insn_out_execute),
1e66d5d1	311	.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
fdecc897	312	.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
7947b9c7	313	assign execute_out_backflush = jmp;
c65110a8	314
1d97a095	315	assign cp_insn = insn_out_execute;
c65110a8	316	Memory memory(
a4f724e6	317	.clk(clk), .Nrst(~rst),
ab7ee9fc	318	/* stall? */ .flush(writeback_out_backflush),
b455d481 JW	319	.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
b455d481 JW	320	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
a7297aa5	321	.st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),
c65110a8 JW	322	.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
c65110a8 JW	323	.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
fdecc897	324	.spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
c65110a8 JW	325	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
	326	.outstall(stall_cause_memory), .outbubble(bubble_out_memory),
	327	.outpc(pc_out_memory), .outinsn(insn_out_memory),
	328	.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
43e4332c	329	.out_write_data(memory_out_write_data),
ab7ee9fc	330	.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
fdecc897	331	.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
1d97a095 JW	332
	333	Terminal terminal(
	334	.clk(clk),
	335	.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
fd003c7a JW	336	.cp_read(cp_read_terminal), .cp_write(cp_write)
	337	`ifdef verilator
	338	`else
	339	, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
	340	`endif
	341	);
ab7ee9fc JW	342
	343	Writeback writeback(
	344	.clk(clk),
	345	.inbubble(bubble_out_memory),
	346	.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897	347	.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
ab7ee9fc JW	348	.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
	349	.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
	350	.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	351	assign writeback_out_backflush = jmp_out_writeback;
149bcd1a	352
ff39dfc7	353	reg [31:0] clockno = 0;
90ff449a JW	354	always @(posedge clk)
90ff449a JW	355	begin
ff39dfc7 JW	356	clockno <= clockno + 1;
ff39dfc7 JW	357	$display("------------------------------------------------------------------------------");
a7297aa5	358	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
5ca27949	359	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
db2351c4	360	$display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
3550fbf2	361	$display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8	362	$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc	363	$display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a	364	end
ee406839	365	endmodule