Issue: Fix pipe names.
[firearm.git] / system.v
1 `define BUS_ICACHE 1
2 `define BUS_DCACHE 0
3
4 module System(input clk, input rst
5 `ifdef verilator
6 `else
7         , output wire [8:0] sys_odata,
8         input [8:0] sys_idata,
9         output wire sys_tookdata
10 `endif
11         );
12         
13         wire [7:0] bus_req;
14         wire [7:0] bus_ack;
15         wire [31:0] bus_addr;
16         wire [31:0] bus_rdata;
17         wire [31:0] bus_wdata;
18         wire bus_rd, bus_wr;
19         wire bus_ready;
20
21         wire bus_req_icache;
22         wire bus_req_dcache;
23         assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
24         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
25         wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
26         
27         wire [31:0] bus_addr_icache;
28         wire [31:0] bus_wdata_icache;
29         wire bus_rd_icache;
30         wire bus_wr_icache;
31         
32         wire [31:0] bus_addr_dcache;
33         wire [31:0] bus_wdata_dcache;
34         wire bus_rd_dcache;
35         wire bus_wr_dcache;
36         
37         wire [31:0] bus_rdata_blockram;
38         wire bus_ready_blockram;
39         
40         assign bus_addr = bus_addr_icache | bus_addr_dcache;
41         assign bus_rdata = bus_rdata_blockram;
42         assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
43         assign bus_rd = bus_rd_icache | bus_rd_dcache;
44         assign bus_wr = bus_wr_icache | bus_wr_dcache;
45         assign bus_ready = bus_ready_blockram;
46
47         wire [31:0] icache_rd_addr;
48         wire icache_rd_req;
49         wire icache_rd_wait;
50         wire [31:0] icache_rd_data;
51         
52         wire [31:0] dcache_addr;
53         wire dcache_rd_req, dcache_wr_req;
54         wire dcache_rw_wait;
55         wire [31:0] dcache_wr_data, dcache_rd_data;
56         
57         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
58         wire decode_out_carry;
59         
60         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
61         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
62         wire regfile_write;
63         wire [3:0] regfile_write_reg;
64         wire [31:0] regfile_write_data;
65         
66         wire execute_out_write_reg;
67         wire [3:0] execute_out_write_num;
68         wire [31:0] execute_out_write_data;
69         wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
70         wire [31:0] execute_out_cpsr, execute_out_spsr;
71         wire execute_out_cpsrup;
72         
73         wire jmp_out_execute, jmp_out_writeback;
74         wire [31:0] jmppc_out_execute, jmppc_out_writeback;
75         wire jmp = jmp_out_execute | jmp_out_writeback;
76         wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
77         
78         wire memory_out_write_reg;
79         wire [3:0] memory_out_write_num;
80         wire [31:0] memory_out_write_data;
81         wire [31:0] memory_out_cpsr, memory_out_spsr;
82         wire memory_out_cpsrup;
83         
84         wire [31:0] writeback_out_cpsr, writeback_out_spsr;
85
86         wire cp_ack_terminal;
87         wire cp_busy_terminal;
88         wire [31:0] cp_read_terminal;
89         
90         wire cp_req;
91         wire [31:0] cp_insn;
92         wire cp_ack = cp_ack_terminal;
93         wire cp_busy = cp_busy_terminal;
94         wire cp_rnw;
95         wire [31:0] cp_read = cp_read_terminal;
96         wire [31:0] cp_write;
97         
98         wire stall_cause_issue;
99         wire stall_cause_execute;
100         wire stall_cause_memory;
101         wire bubble_out_fetch;
102         wire bubble_out_issue;
103         wire bubble_out_execute;
104         wire bubble_out_memory;
105         wire [31:0] insn_out_fetch;
106         wire [31:0] insn_out_issue;
107         wire [31:0] insn_out_execute;
108         wire [31:0] insn_out_memory;
109         wire [31:0] pc_out_fetch;
110         wire [31:0] pc_out_issue;
111         wire [31:0] pc_out_execute;
112         wire [31:0] pc_out_memory;
113         
114         wire Nrst = ~rst;
115         
116         /*AUTOWIRE*/
117         // Beginning of automatic wires (for undeclared instantiated-module outputs)
118         wire            bubble_1a;              // From fetch of Fetch.v
119         wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
120         wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
121         wire            ic__rd_req_0a;          // From fetch of Fetch.v
122         wire            ic__rd_wait_0a;         // From icache of ICache.v
123         wire [31:0]     insn_1a;                // From fetch of Fetch.v
124         wire [31:0]     pc_1a;                  // From fetch of Fetch.v
125         wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
126         wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
127         wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v
128         wire [31:0]     rf__rdata_3_4a;         // From regfile of RegFile.v
129         wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
130         wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
131         wire [3:0]      rf__read_2_1a;          // From decode of Decode.v
132         wire            stall_0a;               // From issue of Issue.v
133         // End of automatics
134
135         wire execute_out_backflush;
136         wire writeback_out_backflush;
137
138         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
139
140         /* XXX reset? */
141         /* ICache AUTO_TEMPLATE (
142                 .clk(clk),
143                 .bus_req(bus_req_icache),
144                 .bus_ack(bus_ack_icache),
145                 .bus_addr(bus_addr_icache),
146                 .bus_rdata(bus_rdata),
147                 .bus_wdata(bus_wdata_icache),
148                 .bus_rd(bus_rd_icache),
149                 .bus_wr(bus_wr_icache),
150                 .bus_ready(bus_ready),
151                 ); */
152         ICache icache(/*AUTOINST*/
153                       // Outputs
154                       .ic__rd_wait_0a   (ic__rd_wait_0a),
155                       .ic__rd_data_1a   (ic__rd_data_1a[31:0]),
156                       .bus_req          (bus_req_icache),        // Templated
157                       .bus_addr         (bus_addr_icache),       // Templated
158                       .bus_wdata        (bus_wdata_icache),      // Templated
159                       .bus_rd           (bus_rd_icache),         // Templated
160                       .bus_wr           (bus_wr_icache),         // Templated
161                       // Inputs
162                       .clk              (clk),                   // Templated
163                       .ic__rd_addr_0a   (ic__rd_addr_0a[31:0]),
164                       .ic__rd_req_0a    (ic__rd_req_0a),
165                       .bus_ack          (bus_ack_icache),        // Templated
166                       .bus_rdata        (bus_rdata),             // Templated
167                       .bus_ready        (bus_ready));            // Templated
168         
169         DCache dcache(
170                 .clk(clk),
171                 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
172                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
173                 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
174                 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
175                 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
176                 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
177
178 `ifdef verilator
179         BigBlockRAM
180 `else
181         BlockRAM
182 `endif
183         blockram(
184                 .clk(clk),
185                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
186                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
187                 .bus_ready(bus_ready_blockram));
188
189         /* Fetch AUTO_TEMPLATE (
190                 .stall_0a(stall_cause_issue),
191                 .jmp_0a(jmp),
192                 .jmppc_0a(jmppc),
193                 );
194         */
195         Fetch fetch(
196                 /*AUTOINST*/
197                     // Outputs
198                     .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
199                     .ic__rd_req_0a      (ic__rd_req_0a),
200                     .bubble_1a          (bubble_1a),
201                     .insn_1a            (insn_1a[31:0]),
202                     .pc_1a              (pc_1a[31:0]),
203                     // Inputs
204                     .clk                (clk),
205                     .Nrst               (Nrst),
206                     .ic__rd_wait_0a     (ic__rd_wait_0a),
207                     .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
208                     .stall_0a           (stall_cause_issue),     // Templated
209                     .jmp_0a             (jmp),                   // Templated
210                     .jmppc_0a           (jmppc));                // Templated
211         
212         /* Issue AUTO_TEMPLATE (
213                 .stall_1a(stall_cause_execute),
214                 .flush(execute_out_backflush | writeback_out_backflush),
215                 .cpsr_1a(writeback_out_cpsr),
216                 .bubble_2a(bubble_out_issue),
217                 .pc_2a(pc_out_issue),
218                 .insn_2a(insn_out_issue),
219                 );
220         */
221         Issue issue(
222                 /*AUTOINST*/
223                     // Outputs
224                     .stall_0a           (stall_0a),
225                     .bubble_2a          (bubble_out_issue),      // Templated
226                     .pc_2a              (pc_out_issue),          // Templated
227                     .insn_2a            (insn_out_issue),        // Templated
228                     // Inputs
229                     .clk                (clk),
230                     .Nrst               (Nrst),
231                     .stall_1a           (stall_cause_execute),   // Templated
232                     .flush              (execute_out_backflush | writeback_out_backflush), // Templated
233                     .bubble_1a          (bubble_1a),
234                     .insn_1a            (insn_1a[31:0]),
235                     .pc_1a              (pc_1a[31:0]),
236                     .cpsr_1a            (writeback_out_cpsr));   // Templated
237         
238         /* RegFile AUTO_TEMPLATE (
239                 .spsr(regfile_spsr),
240                 .write(regfile_write),
241                 .write_reg(regfile_write_reg),
242                 .write_data(regfile_write_data),
243                 );
244         */
245         wire [3:0] rf__read_3_4a;
246         RegFile regfile(
247                 /*AUTOINST*/
248                         // Outputs
249                         .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
250                         .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
251                         .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
252                         .rf__rdata_3_4a (rf__rdata_3_4a[31:0]),
253                         .spsr           (regfile_spsr),          // Templated
254                         // Inputs
255                         .clk            (clk),
256                         .Nrst           (Nrst),
257                         .rf__read_0_1a  (rf__read_0_1a[3:0]),
258                         .rf__read_1_1a  (rf__read_1_1a[3:0]),
259                         .rf__read_2_1a  (rf__read_2_1a[3:0]),
260                         .rf__read_3_4a  (rf__read_3_4a[3:0]),
261                         .write          (regfile_write),         // Templated
262                         .write_reg      (regfile_write_reg),     // Templated
263                         .write_data     (regfile_write_data));   // Templated
264         
265         /* Decode AUTO_TEMPLATE (
266                 .stall(stall_cause_execute),
267                 .incpsr(writeback_out_cpsr),
268                 .inspsr(writeback_out_spsr),
269                 .op0(decode_out_op0),
270                 .op1(decode_out_op1),
271                 .op2(decode_out_op2),
272                 .carry(decode_out_carry),
273                 .outcpsr(decode_out_cpsr),
274                 .outspsr(decode_out_spsr),
275                 );
276         */
277         Decode decode(
278                 /*AUTOINST*/
279                       // Outputs
280                       .op0              (decode_out_op0),        // Templated
281                       .op1              (decode_out_op1),        // Templated
282                       .op2              (decode_out_op2),        // Templated
283                       .carry            (decode_out_carry),      // Templated
284                       .outcpsr          (decode_out_cpsr),       // Templated
285                       .outspsr          (decode_out_spsr),       // Templated
286                       .rf__read_0_1a    (rf__read_0_1a[3:0]),
287                       .rf__read_1_1a    (rf__read_1_1a[3:0]),
288                       .rf__read_2_1a    (rf__read_2_1a[3:0]),
289                       // Inputs
290                       .clk              (clk),
291                       .stall            (stall_cause_execute),   // Templated
292                       .insn_1a          (insn_1a[31:0]),
293                       .pc_1a            (pc_1a[31:0]),
294                       .incpsr           (writeback_out_cpsr),    // Templated
295                       .inspsr           (writeback_out_spsr),    // Templated
296                       .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
297                       .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
298                       .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));
299         
300         Execute execute(
301                 .clk(clk), .Nrst(~rst),
302                 .stall(stall_cause_memory), .flush(writeback_out_backflush),
303                 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
304                 .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
305                 .op2(decode_out_op2), .carry(decode_out_carry),
306                 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
307                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
308                 .write_data(execute_out_write_data),
309                 .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
310                 .outpc(pc_out_execute), .outinsn(insn_out_execute),
311                 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
312                 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
313         assign execute_out_backflush = jmp;
314         
315         assign cp_insn = insn_out_execute;
316         Memory memory(
317                 .clk(clk), .Nrst(~rst),
318                 /* stall? */ .flush(writeback_out_backflush),
319                 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
320                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
321                 .st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),
322                 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
323                 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
324                 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
325                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
326                 .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
327                 .outpc(pc_out_memory), .outinsn(insn_out_memory),
328                 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
329                 .out_write_data(memory_out_write_data),
330                 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
331                 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
332         
333         Terminal terminal(      
334                 .clk(clk),
335                 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
336                 .cp_read(cp_read_terminal), .cp_write(cp_write)
337 `ifdef verilator
338 `else
339                 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
340 `endif
341                 );
342         
343         Writeback writeback(
344                 .clk(clk),
345                 .inbubble(bubble_out_memory),
346                 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
347                 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
348                 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
349                 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
350                 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
351         assign writeback_out_backflush = jmp_out_writeback;
352
353         reg [31:0] clockno = 0;
354         always @(posedge clk)
355         begin
356                 clockno <= clockno + 1;
357                 $display("------------------------------------------------------------------------------");
358                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
359                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
360                 $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
361                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
362                 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
363                 $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
364         end
365 endmodule
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