]> Joshua Wise's Git repositories - mandelfpga.git/history - Main.v
Holy crap, dropped lut count to 7640, and slice count to 4253
[mandelfpga.git] / Main.v
2008-03-28 Joshua WiseHoly crap, dropped lut count to 7640, and slice count...
2008-03-28 Joshua WiseSomething that works
2008-03-28 Joshua Wisepoke the clock with a stick
2008-03-28 Joshua WiseUse the new shnasto PRE_ROLLBACK
2008-03-28 Joshua WiseFix the lame on the multiplier's indentation
2008-03-28 Joshua WiseFix the lame on the multiplier's indentation
2008-03-20 Joshua WiseA define for MAKE_UNIT. And there was much rejoicing.
2008-03-20 Joshua Wisewhat the fuck, this was supposed to get the slice count...
2008-03-20 Joshua WiseClean up and turn the iout and rout into twos comp...
2008-03-19 Joshua WiseReg the init variables -- takes us to 83.842MHz! 8678...
2008-03-19 Joshua WiseDrop a bit from the overflow. Rewrite the assigns.
2008-03-18 Joshua Wise76.025MHz, ship it
2008-03-18 Joshua WiseRemove the DCM cascade unit -- makes it faster to synth...
2008-03-18 Joshua WiseFixed statekick once and for all, hopefully.
2008-03-18 Joshua WiseUse a single DCM unit.
2008-03-18 Joshua WisePotentially fixed triplepump: 75.028MHz, 4596 slices...
2008-03-18 Joshua WiseCut 1 at triple pumping the pipeline
2008-03-17 Joshua WiseOptimization baseline, 77.788MHz, 4894 Slices, 1849...
2008-03-17 Joshua WiseOptimization baseline, 70.493MHz, 4913 Slices, 1843...
2008-03-16 Joshua WiseCorrect whirrrrr
2008-03-16 Joshua WiseBugfix extend init*.
2008-03-16 Joshua WiseWorking 13 bit.
2008-03-15 Joshua WiseInitial revision -- unknown as to whether it works...
This page took 0.110643 seconds and 30 git commands to generate.