always @(posedge clk)
begin
{ovf,out} <=
- (((y[12] ? (x ) : 0) +
- (y[11] ? (x >> 1) : 0) +
- (y[10] ? (x >> 2) : 0)) +
- (((y[9] ? (x >> 3) : 0) +
- (y[8] ? (x >> 4) : 0))+
- ((y[7] ? (x >> 5) : 0) +
- (y[6] ? (x >> 6) : 0))))+
-
- (((y[5] ? (x >> 7) : 0) +
- (y[4] ? (x >> 8) : 0)+
- (y[3] ? (x >> 9) : 0)) +
- ((y[2] ? (x >> 10): 0) +
- (y[1] ? (x >> 11): 0) +
- (y[0] ? (x >> 12): 0)));
+ (((y[12] ? (x ) : 0) +
+ (y[11] ? (x[12:1]) : 0) +
+ (y[10] ? (x[12:2]) : 0)) +
+ (((y[9] ? (x[12:3]) : 0) +
+ (y[8] ? (x[12:4]) : 0)) +
+ ((y[7] ? (x[12:5]) : 0) +
+ (y[6] ? (x[12:6]) : 0))))+
+ (((y[5] ? (x[12:7]) : 0) +
+ (y[4] ? (x[12:8]) : 0) +
+ (y[3] ? (x[12:9]) : 0)) +
+ ((y[2] ? (x[12:10]): 0) +
+ (y[1] ? (x[12:11]): 0) +
+ (y[0] ? (x[12]): 0)));
sign <= xsign ^ ysign;
end
wire [14:0] ri, diff;
wire [15:0] twocdiff;
wire r2sign, i2sign, risign, dsign;
- wire [13:0] bigsum;
+ wire [14:0] bigsum;
wire bigsum_ovf;
reg [12:0] xd, yd;
Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
- assign bigsum = r2[12:0] + i2[12:0];
- assign bigsum_ovf = bigsum[13] | r2[13] | i2[13];
+ assign bigsum = r2[13:0] + i2[13:0];
+ wire shnasto = bigsum[14];
+ wire shnasto2 = // o shi
+ ((r[13] & i[13]) |
+ ((r[13] ^ i[13]) &
+ ((r[12] & i[12]) |
+ ((r[12] ^ i[12]) &
+ ((r[11] & i[11]) |
+ ((r[11] ^ i[11]) &
+ ((r[10] & i[10]) |
+ ((r[10] ^ i[10]) &
+ ((r[ 9] & i[ 9]) |
+ ((r[ 9] ^ i[ 9]) &
+ ((r[ 8] & i[ 8]) |
+ ((r[ 8] ^ i[ 8]) &
+ ((r[ 7] & i[ 7]) |
+ ((r[ 7] ^ i[ 7]) &
+ ((r[ 6] & i[ 6]) |
+ ((r[ 6] ^ i[ 6]) &
+ ((r[ 5] & i[ 5]) |
+ ((r[ 5] ^ i[ 5]) &
+ ((r[ 4] & i[ 4]) |
+ ((r[ 4] ^ i[ 4]) &
+ ((r[ 3] & i[ 3]) |
+ ((r[ 3] ^ i[ 3]) &
+ ((r[ 2] & i[ 2]) |
+ ((r[ 2] ^ i[ 2]) &
+ ((r[ 1] & i[ 1]) |
+ ((r[ 1] ^ i[ 1]) &
+ (r[ 0] & i[ 0])
+ ))))))))))))))))))))))))));
+ assign bigsum_ovf = shnasto;
assign twocdiff = r2 - i2;
assign diff = twocdiff[15] ? -twocdiff : twocdiff;
input left, right, up, down, rst, cycle, logooff,
input [2:0] scale);
- wire pixclk, mclk, gclk2, clk;
+ wire pixclk, mclk, clk;
wire dcm1ok, dcm2ok;
assign dcmok = dcm1ok && dcm2ok;