mandelfpga.git
17 months agoadd comment and sim build rule master
Chris Lu [Thu, 25 Jun 2020 12:06:57 +0000 (07:06 -0500)]
add comment and sim build rule

13 years agoAdd the UCF.
Joshua Wise [Wed, 9 Jul 2008 17:49:05 +0000 (13:49 -0400)]
Add the UCF.

13 years agoAdded logo.readmemb
Joshua Wise [Wed, 9 Jul 2008 17:39:45 +0000 (13:39 -0400)]
Added logo.readmemb

13 years agoOne more fixup
Joshua Wise [Wed, 9 Jul 2008 17:38:16 +0000 (13:38 -0400)]
One more fixup

13 years agoAdd needed files for build; I r retard.
Joshua Wise [Wed, 9 Jul 2008 17:36:41 +0000 (13:36 -0400)]
Add needed files for build; I r retard.

13 years agoadded mandelsim.c
Christopher Lu [Wed, 9 Jul 2008 04:24:51 +0000 (00:24 -0400)]
added mandelsim.c

13 years agoAdd another bit.
Joshua Wise [Wed, 9 Jul 2008 04:13:40 +0000 (00:13 -0400)]
Add another bit.

13 years agoConvert to xc3s1200e, add more units, prepare to add another bit.
Joshua Wise [Wed, 9 Jul 2008 03:10:13 +0000 (23:10 -0400)]
Convert to xc3s1200e, add more units, prepare to add another bit.

13 years agobring in the make buildsystem for MandelFPGA
Joshua Wise [Tue, 8 Jul 2008 03:20:59 +0000 (23:20 -0400)]
bring in the make buildsystem for MandelFPGA

13 years agobring in the make buildsystem for MandelFPGA
Joshua Wise [Tue, 8 Jul 2008 03:20:56 +0000 (23:20 -0400)]
bring in the make buildsystem for MandelFPGA

13 years agoAdd support for Verilator
Joshua Wise [Thu, 19 Jun 2008 03:29:20 +0000 (23:29 -0400)]
Add support for Verilator

13 years agoHoly crap, dropped lut count to 7640, and slice count to 4253
Joshua Wise [Fri, 28 Mar 2008 23:20:21 +0000 (19:20 -0400)]
Holy crap, dropped lut count to 7640, and slice count to 4253

13 years agoProd/cons-ify readout so it can do realtime
Joshua Wise [Fri, 28 Mar 2008 21:31:07 +0000 (17:31 -0400)]
Prod/cons-ify readout so it can do realtime

13 years agoAdd readout
Joshua Wise [Fri, 28 Mar 2008 20:28:41 +0000 (16:28 -0400)]
Add readout

13 years agoSomething that works
Joshua Wise [Fri, 28 Mar 2008 07:13:27 +0000 (03:13 -0400)]
Something that works

13 years agonew ctoreadmemb
Joshua Wise [Fri, 28 Mar 2008 07:05:38 +0000 (03:05 -0400)]
new ctoreadmemb

13 years agopoke the clock with a stick
Joshua Wise [Fri, 28 Mar 2008 06:57:28 +0000 (02:57 -0400)]
poke the clock with a stick

13 years agoUse the new shnasto PRE_ROLLBACK
Joshua Wise [Fri, 28 Mar 2008 06:13:07 +0000 (02:13 -0400)]
Use the new shnasto

13 years agoFix the lame on the multiplier's indentation
Joshua Wise [Fri, 28 Mar 2008 05:50:41 +0000 (01:50 -0400)]
Fix the lame on the multiplier's indentation

13 years agoFix the lame on the multiplier's indentation
Joshua Wise [Fri, 28 Mar 2008 05:50:20 +0000 (01:50 -0400)]
Fix the lame on the multiplier's indentation

13 years agoA define for MAKE_UNIT. And there was much rejoicing.
Joshua Wise [Thu, 20 Mar 2008 18:41:27 +0000 (14:41 -0400)]
A define for MAKE_UNIT.  And there was much rejoicing.

13 years agowhat the fuck, this was supposed to get the slice count down, instead it's up to...
Joshua Wise [Thu, 20 Mar 2008 18:28:45 +0000 (14:28 -0400)]
what the fuck, this was supposed to get the slice count down, instead it's up to 4716\!

13 years agoClean up and turn the iout and rout into twos comp. I think this made our slice...
Joshua Wise [Thu, 20 Mar 2008 18:19:46 +0000 (14:19 -0400)]
Clean up and turn the iout and rout into twos comp.  I think this made our slice count a little worse, but oh well. 4709 postsynth

13 years agoReg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.
Joshua Wise [Wed, 19 Mar 2008 07:01:45 +0000 (03:01 -0400)]
Reg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.

13 years agoDrop a bit from the overflow. Rewrite the assigns.
Joshua Wise [Wed, 19 Mar 2008 06:29:07 +0000 (02:29 -0400)]
Drop a bit from the overflow.  Rewrite the assigns.

13 years ago76.025MHz, ship it
Joshua Wise [Tue, 18 Mar 2008 21:29:26 +0000 (17:29 -0400)]
76.025MHz, ship it

13 years agoRemove the DCM cascade unit -- makes it faster to synthesize
Joshua Wise [Tue, 18 Mar 2008 06:18:25 +0000 (02:18 -0400)]
Remove the DCM cascade unit -- makes it faster to synthesize

13 years agoFixed statekick once and for all, hopefully.
Joshua Wise [Tue, 18 Mar 2008 05:30:45 +0000 (01:30 -0400)]
Fixed statekick once and for all, hopefully.

13 years agoUse a single DCM unit.
Joshua Wise [Tue, 18 Mar 2008 05:04:26 +0000 (01:04 -0400)]
Use a single DCM unit.

13 years agoPotentially fixed triplepump: 75.028MHz, 4596 slices, 8537 LUTs, 1805 ffs
Joshua Wise [Tue, 18 Mar 2008 04:07:45 +0000 (00:07 -0400)]
Potentially fixed triplepump: 75.028MHz, 4596 slices, 8537 LUTs, 1805 ffs

13 years agoCut 1 at triple pumping the pipeline
Joshua Wise [Tue, 18 Mar 2008 03:22:58 +0000 (23:22 -0400)]
Cut 1 at triple pumping the pipeline

13 years agoOptimization baseline, 77.788MHz, 4894 Slices, 1849 slice FFs, 9078 LUTs
Joshua Wise [Mon, 17 Mar 2008 22:32:28 +0000 (18:32 -0400)]
Optimization baseline, 77.788MHz, 4894 Slices, 1849 slice FFs, 9078 LUTs

13 years agoOptimization baseline, 70.493MHz, 4913 Slices, 1843 slice FFs, 9065 LUTs
Joshua Wise [Mon, 17 Mar 2008 21:59:04 +0000 (17:59 -0400)]
Optimization baseline, 70.493MHz, 4913 Slices, 1843 slice FFs, 9065 LUTs

13 years agoCorrect whirrrrr
Joshua Wise [Sun, 16 Mar 2008 03:19:58 +0000 (23:19 -0400)]
Correct whirrrrr

13 years agoBugfix extend init*.
Joshua Wise [Sun, 16 Mar 2008 00:32:02 +0000 (20:32 -0400)]
Bugfix extend init*.

13 years agoWorking 13 bit.
Joshua Wise [Sun, 16 Mar 2008 00:22:23 +0000 (20:22 -0400)]
Working 13 bit.

13 years agoInitial revision -- unknown as to whether it works, post-precision increment.
Joshua Wise [Sat, 15 Mar 2008 22:17:46 +0000 (18:17 -0400)]
Initial revision -- unknown as to whether it works, post-precision increment.

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