reg statekick = 0; // State needs to be kicked back to 3'b010 on the next mclk.
// This is guaranteed to converge after two pixclks.
- //always @(negedge mclk)
- // if (pixclk && !typethea) begin
- // typethea <= 1;
- // statekick <= 1;
- // end else if (typethea) begin // This is the edge of the falling anus.
- // typethea <= 0;
- // statekick <= 0;
- // end
+ always @(negedge mclk)
+ if (pixclk && !statekick) begin
+ statekick <= 1;
+ end else if (statekick) begin // This is the edge of the falling anus.
+ statekick <= 0;
+ end
always @(posedge mclk)
begin
wire pixclk, mclk, gclk2, clk;
wire dcm1ok, dcm2ok;
- assign dcmok = dcm1ok && dcm2ok;
+ //assign dcmok = dcm1ok && dcm2ok;
+
+ //IBUFG typeA(.O(clk), .I(gclk));
- IBUFG typeA(.O(clk), .I(gclk));
+ //pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+ // .CLKIN_IN(clk),
+ // .CLKFX_OUT(pixclk),
+ // .LOCKED_OUT(dcm1ok)
+ // );
- pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
- .CLKIN_IN(clk),
- .CLKFX_OUT(pixclk),
- .LOCKED_OUT(dcm1ok)
- );
+ //mandelDCM dcm2(
+ // .CLKIN_IN(clk),
+ // .CLKFX_OUT(mclk),
+ // .LOCKED_OUT(dcm2ok)
+ // );
- mandelDCM dcm2(
- .CLKIN_IN(clk),
- .CLKFX_OUT(mclk),
- .LOCKED_OUT(dcm2ok)
- );
+ mainDCM dcm (
+ .U1_CLKIN_IN(gclk),
+ .U1_CLKDV_OUT(pixclk),
+ .U2_CLKFX_OUT(mclk),
+ .U2_LOCKED_OUT(dcmok)
+ );
wire border;
wire [11:0] x, y;