Global: More re-piping, and a bugfix for a bug recently introduced. (Regressions...
[firearm.git] / system.v
CommitLineData
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1`define BUS_ICACHE 1
2`define BUS_DCACHE 0
ee406839 3
a4f724e6 4module System(input clk, input rst
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5`ifdef verilator
6`else
7 , output wire [8:0] sys_odata,
8 input [8:0] sys_idata,
9 output wire sys_tookdata
10`endif
11 );
12
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13 wire [7:0] bus_req;
14 wire [7:0] bus_ack;
15 wire [31:0] bus_addr;
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16 wire [31:0] bus_rdata;
17 wire [31:0] bus_wdata;
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18 wire bus_rd, bus_wr;
19 wire bus_ready;
45fa96c0 20
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21 wire bus_req_icache;
22 wire bus_req_dcache;
e3a9107a 23 assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839 24 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381 25 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0 26
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27 wire [31:0] bus_addr_icache;
28 wire [31:0] bus_wdata_icache;
29 wire bus_rd_icache;
30 wire bus_wr_icache;
31
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32 wire [31:0] bus_addr_dcache;
33 wire [31:0] bus_wdata_dcache;
34 wire bus_rd_dcache;
35 wire bus_wr_dcache;
36
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37 wire [31:0] bus_rdata_blockram;
38 wire bus_ready_blockram;
39
03f45381 40 assign bus_addr = bus_addr_icache | bus_addr_dcache;
a0bb35e7 41 assign bus_rdata = bus_rdata_blockram;
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42 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
43 assign bus_rd = bus_rd_icache | bus_rd_dcache;
44 assign bus_wr = bus_wr_icache | bus_wr_dcache;
a0bb35e7 45 assign bus_ready = bus_ready_blockram;
149bcd1a 46
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47 wire [31:0] icache_rd_addr;
48 wire icache_rd_req;
49 wire icache_rd_wait;
50 wire [31:0] icache_rd_data;
09e28f01 51
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52 wire [31:0] dcache_addr;
53 wire dcache_rd_req, dcache_wr_req;
54 wire dcache_rw_wait;
55 wire [31:0] dcache_wr_data, dcache_rd_data;
56
ab7ee9fc 57 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610 58 wire decode_out_carry;
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59
60 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
61 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
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62 wire regfile_write;
63 wire [3:0] regfile_write_reg;
64 wire [31:0] regfile_write_data;
c65110a8 65
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66 wire execute_out_write_reg;
67 wire [3:0] execute_out_write_num;
68 wire [31:0] execute_out_write_data;
c65110a8 69 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1 70 wire [31:0] execute_out_cpsr, execute_out_spsr;
fdecc897 71 wire execute_out_cpsrup;
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72
73 wire jmp_out_execute, jmp_out_writeback;
74 wire [31:0] jmppc_out_execute, jmppc_out_writeback;
75 wire jmp = jmp_out_execute | jmp_out_writeback;
76 wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
5ca27949 77
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78 wire memory_out_write_reg;
79 wire [3:0] memory_out_write_num;
80 wire [31:0] memory_out_write_data;
ab7ee9fc 81 wire [31:0] memory_out_cpsr, memory_out_spsr;
fdecc897 82 wire memory_out_cpsrup;
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83
84 wire [31:0] writeback_out_cpsr, writeback_out_spsr;
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85
86 wire cp_ack_terminal;
87 wire cp_busy_terminal;
88 wire [31:0] cp_read_terminal;
c65110a8 89
43e4332c 90 wire cp_req;
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91 wire [31:0] cp_insn;
92 wire cp_ack = cp_ack_terminal;
93 wire cp_busy = cp_busy_terminal;
43e4332c 94 wire cp_rnw;
1d97a095 95 wire [31:0] cp_read = cp_read_terminal;
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96 wire [31:0] cp_write;
97
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98 wire stall_cause_issue;
99 wire stall_cause_execute;
100 wire stall_cause_memory;
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101 wire bubble_out_fetch;
102 wire bubble_out_issue;
2393422a 103 wire bubble_out_execute;
c65110a8 104 wire bubble_out_memory;
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105 wire [31:0] insn_out_fetch;
106 wire [31:0] insn_out_issue;
2393422a 107 wire [31:0] insn_out_execute;
c65110a8 108 wire [31:0] insn_out_memory;
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109 wire [31:0] pc_out_fetch;
110 wire [31:0] pc_out_issue;
2393422a 111 wire [31:0] pc_out_execute;
c65110a8 112 wire [31:0] pc_out_memory;
2bf779cf 113
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114 wire Nrst = ~rst;
115
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116 /*AUTOWIRE*/
117 // Beginning of automatic wires (for undeclared instantiated-module outputs)
a7297aa5 118 wire bubble_1a; // From fetch of Fetch.v
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119 wire bubble_2a; // From issue of Issue.v
120 wire carry_2a; // From decode of Decode.v
121 wire [31:0] cpsr_2a; // From decode of Decode.v
2bf779cf 122 wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
3c947a99 123 wire [31:0] ic__rd_data_1a; // From icache of ICache.v
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124 wire ic__rd_req_0a; // From fetch of Fetch.v
125 wire ic__rd_wait_0a; // From icache of ICache.v
a7297aa5 126 wire [31:0] insn_1a; // From fetch of Fetch.v
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127 wire [31:0] insn_2a; // From issue of Issue.v
128 wire [31:0] op0_2a; // From decode of Decode.v
129 wire [31:0] op1_2a; // From decode of Decode.v
130 wire [31:0] op2_2a; // From decode of Decode.v
a7297aa5 131 wire [31:0] pc_1a; // From fetch of Fetch.v
8c1ba494 132 wire [31:0] pc_2a; // From issue of Issue.v
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133 wire [31:0] rf__rdata_0_1a; // From regfile of RegFile.v
134 wire [31:0] rf__rdata_1_1a; // From regfile of RegFile.v
135 wire [31:0] rf__rdata_2_1a; // From regfile of RegFile.v
136 wire [31:0] rf__rdata_3_4a; // From regfile of RegFile.v
137 wire [3:0] rf__read_0_1a; // From decode of Decode.v
138 wire [3:0] rf__read_1_1a; // From decode of Decode.v
139 wire [3:0] rf__read_2_1a; // From decode of Decode.v
8c1ba494 140 wire [31:0] spsr_2a; // From decode of Decode.v
ae457ae9 141 wire stall_0a; // From issue of Issue.v
2bf779cf 142 // End of automatics
149bcd1a 143
7947b9c7 144 wire execute_out_backflush;
ab7ee9fc 145 wire writeback_out_backflush;
c2b9d4b7 146
ee406839 147 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7 148
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149 /* XXX reset? */
150 /* ICache AUTO_TEMPLATE (
a0bb35e7 151 .clk(clk),
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152 .bus_req(bus_req_icache),
153 .bus_ack(bus_ack_icache),
154 .bus_addr(bus_addr_icache),
155 .bus_rdata(bus_rdata),
156 .bus_wdata(bus_wdata_icache),
157 .bus_rd(bus_rd_icache),
158 .bus_wr(bus_wr_icache),
159 .bus_ready(bus_ready),
160 ); */
161 ICache icache(/*AUTOINST*/
162 // Outputs
163 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 164 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
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165 .bus_req (bus_req_icache), // Templated
166 .bus_addr (bus_addr_icache), // Templated
167 .bus_wdata (bus_wdata_icache), // Templated
168 .bus_rd (bus_rd_icache), // Templated
169 .bus_wr (bus_wr_icache), // Templated
170 // Inputs
171 .clk (clk), // Templated
172 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
173 .ic__rd_req_0a (ic__rd_req_0a),
174 .bus_ack (bus_ack_icache), // Templated
175 .bus_rdata (bus_rdata), // Templated
176 .bus_ready (bus_ready)); // Templated
45fa96c0 177
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178 DCache dcache(
179 .clk(clk),
180 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
181 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
182 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
183 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
184 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
185 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
186
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187`ifdef verilator
188 BigBlockRAM
189`else
190 BlockRAM
191`endif
192 blockram(
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193 .clk(clk),
194 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
195 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
196 .bus_ready(bus_ready_blockram));
197
2bf779cf 198 /* Fetch AUTO_TEMPLATE (
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199 .jmp_0a(jmp),
200 .jmppc_0a(jmppc),
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201 );
202 */
203 Fetch fetch(
204 /*AUTOINST*/
205 // Outputs
206 .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
207 .ic__rd_req_0a (ic__rd_req_0a),
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208 .bubble_1a (bubble_1a),
209 .insn_1a (insn_1a[31:0]),
210 .pc_1a (pc_1a[31:0]),
2bf779cf 211 // Inputs
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212 .clk (clk),
213 .Nrst (Nrst),
2bf779cf 214 .ic__rd_wait_0a (ic__rd_wait_0a),
3c947a99 215 .ic__rd_data_1a (ic__rd_data_1a[31:0]),
8c1ba494 216 .stall_0a (stall_0a),
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217 .jmp_0a (jmp), // Templated
218 .jmppc_0a (jmppc)); // Templated
09e28f01 219
a7297aa5 220 /* Issue AUTO_TEMPLATE (
ae457ae9 221 .stall_1a(stall_cause_execute),
8c1ba494 222 .flush_1a(execute_out_backflush | writeback_out_backflush),
ae457ae9 223 .cpsr_1a(writeback_out_cpsr),
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224 );
225 */
09e28f01 226 Issue issue(
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227 /*AUTOINST*/
228 // Outputs
ae457ae9 229 .stall_0a (stall_0a),
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230 .bubble_2a (bubble_2a),
231 .pc_2a (pc_2a[31:0]),
232 .insn_2a (insn_2a[31:0]),
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233 // Inputs
234 .clk (clk),
235 .Nrst (Nrst),
ae457ae9 236 .stall_1a (stall_cause_execute), // Templated
8c1ba494 237 .flush_1a (execute_out_backflush | writeback_out_backflush), // Templated
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238 .bubble_1a (bubble_1a),
239 .insn_1a (insn_1a[31:0]),
240 .pc_1a (pc_1a[31:0]),
ae457ae9 241 .cpsr_1a (writeback_out_cpsr)); // Templated
90ff449a 242
a7297aa5 243 /* RegFile AUTO_TEMPLATE (
ab7ee9fc 244 .spsr(regfile_spsr),
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245 .write(regfile_write),
246 .write_reg(regfile_write_reg),
247 .write_data(regfile_write_data),
248 );
249 */
250 wire [3:0] rf__read_3_4a;
251 RegFile regfile(
252 /*AUTOINST*/
253 // Outputs
254 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
255 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
256 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
257 .rf__rdata_3_4a (rf__rdata_3_4a[31:0]),
258 .spsr (regfile_spsr), // Templated
259 // Inputs
260 .clk (clk),
261 .Nrst (Nrst),
262 .rf__read_0_1a (rf__read_0_1a[3:0]),
263 .rf__read_1_1a (rf__read_1_1a[3:0]),
264 .rf__read_2_1a (rf__read_2_1a[3:0]),
265 .rf__read_3_4a (rf__read_3_4a[3:0]),
266 .write (regfile_write), // Templated
267 .write_reg (regfile_write_reg), // Templated
268 .write_data (regfile_write_data)); // Templated
5ca27949 269
a7297aa5 270 /* Decode AUTO_TEMPLATE (
e74c7936 271 .stall(stall_cause_execute),
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272 .cpsr_1a(writeback_out_cpsr),
273 .spsr_1a(writeback_out_spsr),
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274 );
275 */
276 Decode decode(
277 /*AUTOINST*/
278 // Outputs
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279 .op0_2a (op0_2a[31:0]),
280 .op1_2a (op1_2a[31:0]),
281 .op2_2a (op2_2a[31:0]),
282 .carry_2a (carry_2a),
283 .cpsr_2a (cpsr_2a[31:0]),
284 .spsr_2a (spsr_2a[31:0]),
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285 .rf__read_0_1a (rf__read_0_1a[3:0]),
286 .rf__read_1_1a (rf__read_1_1a[3:0]),
287 .rf__read_2_1a (rf__read_2_1a[3:0]),
288 // Inputs
289 .clk (clk),
290 .stall (stall_cause_execute), // Templated
291 .insn_1a (insn_1a[31:0]),
292 .pc_1a (pc_1a[31:0]),
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293 .cpsr_1a (writeback_out_cpsr), // Templated
294 .spsr_1a (writeback_out_spsr), // Templated
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295 .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
296 .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
297 .rf__rdata_2_1a (rf__rdata_2_1a[31:0]));
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298
299 /* Execute AUTO_TEMPLATE (
300 .stall_2a(stall_cause_memory),
301 .flush(writeback_out_backflush),
302 .outstall_2a(stall_cause_execute),
303 .bubble_3a(bubble_out_execute),
304 .write_reg_3a(execute_out_write_reg),
305 .write_num_3a(execute_out_write_num),
306 .write_data_3a(execute_out_write_data),
307 .jmp_2a(jmp_out_execute),
308 .jmppc_2a(jmppc_out_execute),
309 .pc_3a(pc_out_execute),
310 .insn_3a(insn_out_execute),
311 .op0_3a(execute_out_op0),
312 .op1_3a(execute_out_op1),
313 .op2_3a(execute_out_op2),
314 .outcpsr(execute_out_cpsr),
315 .outspsr(execute_out_spsr),
316 .outcpsrup(execute_out_cpsrup),
317 );
318 */
bc572c5f 319 Execute execute(
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320 /*AUTOINST*/
321 // Outputs
322 .outstall_2a (stall_cause_execute), // Templated
323 .bubble_3a (bubble_out_execute), // Templated
324 .outcpsr (execute_out_cpsr), // Templated
325 .outspsr (execute_out_spsr), // Templated
326 .outcpsrup (execute_out_cpsrup), // Templated
327 .write_reg_3a (execute_out_write_reg), // Templated
328 .write_num_3a (execute_out_write_num), // Templated
329 .write_data_3a (execute_out_write_data), // Templated
330 .jmppc_2a (jmppc_out_execute), // Templated
331 .jmp_2a (jmp_out_execute), // Templated
332 .pc_3a (pc_out_execute), // Templated
333 .insn_3a (insn_out_execute), // Templated
334 .op0_3a (execute_out_op0), // Templated
335 .op1_3a (execute_out_op1), // Templated
336 .op2_3a (execute_out_op2), // Templated
337 // Inputs
338 .clk (clk),
339 .Nrst (Nrst),
340 .stall_2a (stall_cause_memory), // Templated
341 .flush (writeback_out_backflush), // Templated
342 .bubble_2a (bubble_2a),
343 .pc_2a (pc_2a[31:0]),
344 .insn_2a (insn_2a[31:0]),
345 .cpsr_2a (cpsr_2a[31:0]),
346 .spsr_2a (spsr_2a[31:0]),
347 .op0_2a (op0_2a[31:0]),
348 .op1_2a (op1_2a[31:0]),
349 .op2_2a (op2_2a[31:0]),
350 .carry_2a (carry_2a));
7947b9c7 351 assign execute_out_backflush = jmp;
c65110a8 352
1d97a095 353 assign cp_insn = insn_out_execute;
c65110a8 354 Memory memory(
a4f724e6 355 .clk(clk), .Nrst(~rst),
ab7ee9fc 356 /* stall? */ .flush(writeback_out_backflush),
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357 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
358 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
a7297aa5 359 .st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),
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360 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
361 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
fdecc897 362 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
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363 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
364 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
365 .outpc(pc_out_memory), .outinsn(insn_out_memory),
366 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
43e4332c 367 .out_write_data(memory_out_write_data),
ab7ee9fc 368 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
fdecc897 369 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
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370
371 Terminal terminal(
372 .clk(clk),
373 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
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374 .cp_read(cp_read_terminal), .cp_write(cp_write)
375`ifdef verilator
376`else
377 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
378`endif
379 );
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380
381 Writeback writeback(
382 .clk(clk),
383 .inbubble(bubble_out_memory),
384 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
fdecc897 385 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
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386 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
387 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
388 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
389 assign writeback_out_backflush = jmp_out_writeback;
149bcd1a 390
ff39dfc7 391 reg [31:0] clockno = 0;
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392 always @(posedge clk)
393 begin
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394 clockno <= clockno + 1;
395 $display("------------------------------------------------------------------------------");
a7297aa5 396 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
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397 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
398 $display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
3550fbf2 399 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8 400 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc 401 $display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a 402 end
ee406839 403endmodule
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