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Commit | Line | Data |
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b3bb2fb8 CL |
1 | `include "ARM_Constants.v" |
2 | ||
3 | module Memory( | |
4 | input clk, | |
5 | input Nrst, | |
b3bb2fb8 | 6 | |
ab7ee9fc JW |
7 | input flush, |
8 | ||
b3bb2fb8 CL |
9 | /* bus interface */ |
10 | output reg [31:0] busaddr, | |
11 | output reg rd_req, | |
12 | output reg wr_req, | |
13 | input rw_wait, | |
14 | output reg [31:0] wr_data, | |
15 | input [31:0] rd_data, | |
9fc6c23c | 16 | output reg [2:0] data_size, |
b3bb2fb8 CL |
17 | |
18 | /* regfile interface */ | |
19 | output reg [3:0] st_read, | |
20 | input [31:0] st_data, | |
a02ca509 | 21 | |
979f2bd7 JW |
22 | /* Coprocessor interface */ |
23 | output reg cp_req, | |
24 | input cp_ack, | |
25 | input cp_busy, | |
804dc0bc | 26 | output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */ |
43e4332c JW |
27 | input [31:0] cp_read, |
28 | output reg [31:0] cp_write, | |
979f2bd7 | 29 | |
a02ca509 JW |
30 | /* stage inputs */ |
31 | input inbubble, | |
32 | input [31:0] pc, | |
33 | input [31:0] insn, | |
e68b2378 JW |
34 | input [31:0] op0, |
35 | input [31:0] op1, | |
6d0f9d82 | 36 | input [31:0] op2, |
efd1aa13 CL |
37 | input [31:0] spsr, |
38 | input [31:0] cpsr, | |
a02ca509 JW |
39 | input write_reg, |
40 | input [3:0] write_num, | |
41 | input [31:0] write_data, | |
b3bb2fb8 | 42 | |
a02ca509 JW |
43 | /* outputs */ |
44 | output reg outstall, | |
45 | output reg outbubble, | |
b3bb2fb8 | 46 | output reg [31:0] outpc, |
a02ca509 JW |
47 | output reg [31:0] outinsn, |
48 | output reg out_write_reg = 1'b0, | |
49 | output reg [3:0] out_write_num = 4'bxxxx, | |
efd1aa13 | 50 | output reg [31:0] out_write_data = 32'hxxxxxxxx, |
ab7ee9fc JW |
51 | output reg [31:0] outspsr = 32'hxxxxxxxx, |
52 | output reg [31:0] outcpsr = 32'hxxxxxxxx | |
a02ca509 | 53 | ); |
b3bb2fb8 | 54 | |
efd1aa13 | 55 | reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr; |
666ceb03 | 56 | reg [31:0] prevaddr; |
e08b748a | 57 | reg [3:0] next_regsel, cur_reg, prev_reg; |
9a0d0e43 | 58 | reg next_writeback; |
e08b748a | 59 | |
804dc0bc JW |
60 | reg next_outbubble; |
61 | reg next_write_reg; | |
62 | reg [3:0] next_write_num; | |
63 | reg [31:0] next_write_data; | |
74d3729c | 64 | |
9a0d0e43 | 65 | reg [1:0] lsr_state = 2'b01, next_lsr_state; |
666ceb03 CL |
66 | reg [31:0] align_s1, align_s2, align_rddata; |
67 | ||
68 | reg [1:0] lsrh_state = 2'b01, next_lsrh_state; | |
69 | reg [31:0] lsrh_rddata; | |
70 | reg [15:0] lsrh_rddata_s1; | |
71 | reg [7:0] lsrh_rddata_s2; | |
9a0d0e43 | 72 | |
b783a475 | 73 | reg [15:0] regs, next_regs; |
9a0d0e43 | 74 | reg [2:0] lsm_state = 3'b001, next_lsm_state; |
b114e03f | 75 | reg [5:0] offset, prev_offset, offset_sel; |
74d3729c | 76 | |
9a0d0e43 CL |
77 | reg [31:0] swp_oldval, next_swp_oldval; |
78 | reg [1:0] swp_state = 2'b01, next_swp_state; | |
a02ca509 JW |
79 | |
80 | always @(posedge clk) | |
81 | begin | |
82 | outpc <= pc; | |
83 | outinsn <= insn; | |
c65110a8 JW |
84 | outbubble <= next_outbubble; |
85 | out_write_reg <= next_write_reg; | |
86 | out_write_num <= next_write_num; | |
87 | out_write_data <= next_write_data; | |
e68b2378 | 88 | regs <= next_regs; |
e08b748a | 89 | prev_reg <= cur_reg; |
b114e03f CL |
90 | prev_offset <= offset; |
91 | prev_raddr <= raddr; | |
ab7ee9fc JW |
92 | outcpsr <= next_outcpsr; |
93 | outspsr <= spsr; | |
9a0d0e43 | 94 | swp_state <= next_swp_state; |
666ceb03 CL |
95 | lsm_state <= next_lsm_state; |
96 | lsr_state <= next_lsr_state; | |
97 | lsrh_state <= next_lsrh_state; | |
98 | prevaddr <= addr; | |
a02ca509 | 99 | end |
b3bb2fb8 CL |
100 | |
101 | always @(*) | |
102 | begin | |
666ceb03 | 103 | addr = prevaddr; |
b3bb2fb8 CL |
104 | raddr = 32'hxxxxxxxx; |
105 | rd_req = 1'b0; | |
106 | wr_req = 1'b0; | |
107 | wr_data = 32'hxxxxxxxx; | |
108 | busaddr = 32'hxxxxxxxx; | |
2bcc55d5 | 109 | data_size = 3'bxxx; |
b3bb2fb8 | 110 | outstall = 1'b0; |
a02ca509 JW |
111 | next_write_reg = write_reg; |
112 | next_write_num = write_num; | |
113 | next_write_data = write_data; | |
c65110a8 | 114 | next_outbubble = inbubble; |
9a0d0e43 | 115 | next_regs = regs; |
979f2bd7 | 116 | cp_req = 1'b0; |
43e4332c JW |
117 | cp_rnw = 1'bx; |
118 | cp_write = 32'hxxxxxxxx; | |
b114e03f | 119 | offset = prev_offset; |
ab7ee9fc | 120 | next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr; |
666ceb03 | 121 | lsrh_rddata = 32'hxxxxxxxx; |
9fc6c23c CL |
122 | lsrh_rddata_s1 = 16'hxxxx; |
123 | lsrh_rddata_s2 = 8'hxx; | |
9a0d0e43 CL |
124 | next_lsm_state = lsm_state; |
125 | next_lsr_state = lsr_state; | |
666ceb03 | 126 | next_lsrh_state = lsrh_state; |
9a0d0e43 CL |
127 | next_swp_oldval = swp_oldval; |
128 | next_swp_state = swp_state; | |
129 | cur_reg = prev_reg; | |
9f082c0b | 130 | |
5989b2f5 | 131 | /* XXX shit not given about endianness */ |
ab7ee9fc JW |
132 | if (flush) |
133 | next_outbubble = 1'b1; | |
134 | else casez(insn) | |
5989b2f5 CL |
135 | `DECODE_ALU_SWP: if(!inbubble) begin |
136 | outstall = rw_wait; | |
137 | next_outbubble = rw_wait; | |
138 | busaddr = {op0[31:2], 2'b0}; | |
2bcc55d5 | 139 | data_size = insn[22] ? 3'b001 : 3'b100; |
5989b2f5 CL |
140 | case(swp_state) |
141 | 2'b01: begin | |
142 | rd_req = 1'b1; | |
143 | outstall = 1'b1; | |
144 | if(!rw_wait) begin | |
145 | next_swp_state = 2'b10; | |
146 | next_swp_oldval = rd_data; | |
9a0d0e43 | 147 | end |
9a0d0e43 | 148 | end |
5989b2f5 CL |
149 | 2'b10: begin |
150 | wr_req = 1'b1; | |
2bcc55d5 | 151 | wr_data = insn[22] ? {4{op1[7:0]}} : op1; |
5989b2f5 CL |
152 | next_write_reg = 1'b1; |
153 | next_write_num = insn[15:12]; | |
2bcc55d5 | 154 | next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval; |
5989b2f5 CL |
155 | if(!rw_wait) |
156 | next_swp_state = 2'b01; | |
157 | end | |
158 | default: begin end | |
159 | endcase | |
9a0d0e43 | 160 | end |
666ceb03 CL |
161 | `DECODE_ALU_HDATA_REG, |
162 | `DECODE_ALU_HDATA_IMM: if(!inbubble) begin | |
163 | next_outbubble = rw_wait; | |
164 | outstall = rw_wait; | |
165 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ | |
166 | raddr = insn[24] ? op0 : addr; /* pre/post increment */ | |
167 | busaddr = raddr; | |
168 | /* rotate to correct position */ | |
169 | case(insn[6:5]) | |
170 | 2'b00: begin end /* swp */ | |
171 | 2'b01: begin /* unsigned half */ | |
172 | wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */ | |
2bcc55d5 | 173 | data_size = 3'b010; |
666ceb03 CL |
174 | lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]}; |
175 | end | |
176 | 2'b10: begin /* signed byte */ | |
177 | wr_data = {4{op2[7:0]}}; | |
2bcc55d5 | 178 | data_size = 3'b001; |
666ceb03 CL |
179 | lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0]; |
180 | lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0]; | |
181 | lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2}; | |
182 | end | |
183 | 2'b11: begin /* signed half */ | |
184 | wr_data = {2{op2[15:0]}}; | |
2bcc55d5 | 185 | data_size = 3'b010; |
666ceb03 CL |
186 | lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]}; |
187 | end | |
188 | endcase | |
189 | ||
190 | case(lsrh_state) | |
191 | 2'b01: begin | |
192 | rd_req = insn[20]; | |
193 | wr_req = ~insn[20]; | |
194 | next_write_num = insn[15:12]; | |
195 | next_write_data = lsrh_rddata; | |
196 | if(insn[20]) begin | |
197 | next_write_reg = 1'b1; | |
198 | end | |
199 | if(insn[21] | !insn[24]) begin | |
200 | outstall = 1'b1; | |
201 | if(!rw_wait) | |
202 | next_lsrh_state = 2'b10; | |
203 | end | |
204 | end | |
205 | 2'b10: begin | |
206 | next_write_reg = 1'b1; | |
207 | next_write_num = insn[19:16]; | |
208 | next_write_data = addr; | |
209 | next_lsrh_state = 2'b10; | |
210 | end | |
211 | default: begin end | |
212 | endcase | |
213 | end | |
b3bb2fb8 | 214 | `DECODE_LDRSTR_UNDEFINED: begin end |
5989b2f5 CL |
215 | `DECODE_LDRSTR: if(!inbubble) begin |
216 | next_outbubble = rw_wait; | |
217 | outstall = rw_wait; | |
218 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ | |
219 | raddr = insn[24] ? op0 : addr; /* pre/post increment */ | |
666ceb03 CL |
220 | busaddr = raddr; |
221 | /* rotate to correct position */ | |
5989b2f5 CL |
222 | align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data; |
223 | align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1; | |
224 | /* select byte or word */ | |
225 | align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2; | |
666ceb03 | 226 | wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */ |
2bcc55d5 | 227 | data_size = insn[22] ? 3'b001 : 3'b100; |
5989b2f5 CL |
228 | case(lsr_state) |
229 | 2'b01: begin | |
230 | rd_req = insn[20]; | |
231 | wr_req = ~insn[20]; | |
666ceb03 CL |
232 | next_write_reg = 1'b1; |
233 | next_write_num = insn[15:12]; | |
5989b2f5 | 234 | if(insn[20]) begin |
5989b2f5 | 235 | next_write_data = align_rddata; |
a02ca509 | 236 | end |
666ceb03 | 237 | if(insn[21] | !insn[24]) begin |
5989b2f5 CL |
238 | outstall = 1'b1; |
239 | if(!rw_wait) | |
240 | next_lsr_state = 2'b10; | |
a02ca509 | 241 | end |
b3bb2fb8 | 242 | end |
5989b2f5 CL |
243 | 2'b10: begin |
244 | next_write_reg = 1'b1; | |
245 | next_write_num = insn[19:16]; | |
246 | next_write_data = addr; | |
247 | next_lsr_state = 2'b10; | |
248 | end | |
249 | default: begin end | |
250 | endcase | |
b3bb2fb8 | 251 | end |
5989b2f5 CL |
252 | /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */ |
253 | `DECODE_LDMSTM: if(!inbubble) begin | |
9a0d0e43 CL |
254 | outstall = rw_wait; |
255 | next_outbubble = rw_wait; | |
2bcc55d5 | 256 | data_size = 3'b100; |
9a0d0e43 CL |
257 | case(lsm_state) |
258 | 3'b001: begin | |
b114e03f CL |
259 | // next_regs = insn[23] ? op1[15:0] : op1[0:15]; |
260 | /** verilator can suck my dick */ | |
261 | next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7], | |
262 | op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]}; | |
263 | offset = 6'b0; | |
9a0d0e43 CL |
264 | outstall = 1'b1; |
265 | next_lsm_state = 3'b010; | |
e08b748a | 266 | end |
9a0d0e43 CL |
267 | 3'b010: begin |
268 | rd_req = insn[20]; | |
269 | wr_req = ~insn[20]; | |
9f082c0b CL |
270 | casez(regs) |
271 | 16'b???????????????1: begin | |
e08b748a | 272 | cur_reg = 4'h0; |
b114e03f | 273 | next_regs = {regs[15:1], 1'b0}; |
9f082c0b CL |
274 | end |
275 | 16'b??????????????10: begin | |
e08b748a | 276 | cur_reg = 4'h1; |
b114e03f | 277 | next_regs = {regs[15:2], 2'b0}; |
9f082c0b CL |
278 | end |
279 | 16'b?????????????100: begin | |
e08b748a | 280 | cur_reg = 4'h2; |
b114e03f | 281 | next_regs = {regs[15:3], 3'b0}; |
9f082c0b CL |
282 | end |
283 | 16'b????????????1000: begin | |
e08b748a | 284 | cur_reg = 4'h3; |
b114e03f | 285 | next_regs = {regs[15:4], 4'b0}; |
9f082c0b CL |
286 | end |
287 | 16'b???????????10000: begin | |
e08b748a | 288 | cur_reg = 4'h4; |
b114e03f | 289 | next_regs = {regs[15:5], 5'b0}; |
9f082c0b CL |
290 | end |
291 | 16'b??????????100000: begin | |
e08b748a | 292 | cur_reg = 4'h5; |
b114e03f | 293 | next_regs = {regs[15:6], 6'b0}; |
9f082c0b CL |
294 | end |
295 | 16'b?????????1000000: begin | |
e08b748a | 296 | cur_reg = 4'h6; |
b114e03f | 297 | next_regs = {regs[15:7], 7'b0}; |
9f082c0b CL |
298 | end |
299 | 16'b????????10000000: begin | |
e08b748a | 300 | cur_reg = 4'h7; |
b114e03f | 301 | next_regs = {regs[15:8], 8'b0}; |
9f082c0b CL |
302 | end |
303 | 16'b???????100000000: begin | |
e08b748a | 304 | cur_reg = 4'h8; |
b114e03f | 305 | next_regs = {regs[15:9], 9'b0}; |
9f082c0b CL |
306 | end |
307 | 16'b??????1000000000: begin | |
e08b748a | 308 | cur_reg = 4'h9; |
b114e03f | 309 | next_regs = {regs[15:10], 10'b0}; |
9f082c0b CL |
310 | end |
311 | 16'b?????10000000000: begin | |
e08b748a | 312 | cur_reg = 4'hA; |
b114e03f | 313 | next_regs = {regs[15:11], 11'b0}; |
9f082c0b CL |
314 | end |
315 | 16'b????100000000000: begin | |
e08b748a | 316 | cur_reg = 4'hB; |
b114e03f | 317 | next_regs = {regs[15:12], 12'b0}; |
9f082c0b CL |
318 | end |
319 | 16'b???1000000000000: begin | |
e08b748a | 320 | cur_reg = 4'hC; |
b114e03f | 321 | next_regs = {regs[15:13], 13'b0}; |
9f082c0b CL |
322 | end |
323 | 16'b??10000000000000: begin | |
e08b748a | 324 | cur_reg = 4'hD; |
b114e03f | 325 | next_regs = {regs[15:14], 14'b0}; |
9f082c0b CL |
326 | end |
327 | 16'b?100000000000000: begin | |
e08b748a | 328 | cur_reg = 4'hE; |
b114e03f | 329 | next_regs = {regs[15], 15'b0}; |
9f082c0b CL |
330 | end |
331 | 16'b1000000000000000: begin | |
e08b748a | 332 | cur_reg = 4'hF; |
9f082c0b CL |
333 | next_regs = 16'b0; |
334 | end | |
335 | default: begin | |
e08b748a CL |
336 | cur_reg = 4'hx; |
337 | next_regs = 16'b0; | |
9f082c0b CL |
338 | end |
339 | endcase | |
b114e03f | 340 | cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg; |
efd1aa13 CL |
341 | if(cur_reg == 4'hF && insn[22]) begin |
342 | next_outcpsr = spsr; | |
343 | end | |
b114e03f | 344 | |
9a0d0e43 CL |
345 | if(rw_wait) begin |
346 | next_regs = regs; | |
347 | cur_reg = prev_reg; | |
348 | raddr = prev_raddr; | |
349 | end | |
350 | else begin | |
351 | offset = prev_offset + 6'h4; | |
352 | offset_sel = insn[24] ? offset : prev_offset; | |
353 | raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel}; | |
354 | if(insn[20]) begin | |
355 | next_write_reg = 1'b1; | |
356 | next_write_num = cur_reg; | |
357 | next_write_data = rd_data; | |
358 | end | |
b114e03f CL |
359 | end |
360 | ||
361 | st_read = cur_reg; | |
362 | wr_data = st_data; | |
666ceb03 | 363 | busaddr = raddr; |
9a0d0e43 CL |
364 | |
365 | outstall = 1'b1; | |
366 | ||
367 | if(next_regs == 16'b0) begin | |
368 | next_lsm_state = 3'b100; | |
369 | end | |
370 | end | |
371 | 3'b100: begin | |
372 | next_write_reg = 1'b1; | |
373 | next_write_num = insn[19:16]; | |
374 | next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset}; | |
375 | next_lsm_state = 3'b001; | |
b783a475 | 376 | end |
9a0d0e43 CL |
377 | default: begin end |
378 | endcase | |
b3bb2fb8 | 379 | end |
5989b2f5 | 380 | `DECODE_LDCSTC: if(!inbubble) begin |
43e4332c JW |
381 | $display("WARNING: Unimplemented LDCSTC"); |
382 | end | |
5989b2f5 | 383 | `DECODE_CDP: if(!inbubble) begin |
43e4332c JW |
384 | cp_req = 1; |
385 | if (cp_busy) begin | |
386 | outstall = 1; | |
387 | next_outbubble = 1; | |
388 | end | |
389 | if (!cp_ack) begin | |
390 | /* XXX undefined instruction trap */ | |
391 | $display("WARNING: Possible CDP undefined instruction"); | |
392 | end | |
393 | end | |
5989b2f5 | 394 | `DECODE_MRCMCR: if(!inbubble) begin |
43e4332c JW |
395 | cp_req = 1; |
396 | cp_rnw = insn[20] /* L */; | |
397 | if (insn[20] == 0 /* store to coprocessor */) | |
398 | cp_write = op0; | |
399 | else begin | |
d1d0eb8e JW |
400 | if (insn[15:12] != 4'hF /* Fuck you ARM */) begin |
401 | next_write_reg = 1'b1; | |
402 | next_write_num = insn[15:12]; | |
403 | next_write_data = cp_read; | |
404 | end else | |
405 | next_outcpsr = {cp_read[31:28], cpsr[27:0]}; | |
43e4332c JW |
406 | end |
407 | if (cp_busy) begin | |
408 | outstall = 1; | |
409 | next_outbubble = 1; | |
410 | end | |
411 | if (!cp_ack) begin | |
838e283e | 412 | $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy); |
43e4332c | 413 | end |
838e283e | 414 | $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy); |
43e4332c | 415 | end |
b3bb2fb8 CL |
416 | default: begin end |
417 | endcase | |
418 | end | |
b3bb2fb8 | 419 | endmodule |