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[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8 6
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7 input flush,
8
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9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
16
17 /* regfile interface */
18 output reg [3:0] st_read,
19 input [31:0] st_data,
a02ca509 20
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21 /* Coprocessor interface */
22 output reg cp_req,
23 input cp_ack,
24 input cp_busy,
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25 output cp_rnw, /* 1 = read from CP, 0 = write to CP */
26 input [31:0] cp_read,
27 output reg [31:0] cp_write,
979f2bd7 28
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29 /* stage inputs */
30 input inbubble,
31 input [31:0] pc,
32 input [31:0] insn,
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33 input [31:0] op0,
34 input [31:0] op1,
6d0f9d82 35 input [31:0] op2,
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36 input [31:0] spsr,
37 input [31:0] cpsr,
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38 input write_reg,
39 input [3:0] write_num,
40 input [31:0] write_data,
b3bb2fb8 41
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42 /* outputs */
43 output reg outstall,
44 output reg outbubble,
b3bb2fb8 45 output reg [31:0] outpc,
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46 output reg [31:0] outinsn,
47 output reg out_write_reg = 1'b0,
48 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 49 output reg [31:0] out_write_data = 32'hxxxxxxxx,
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50 output reg [31:0] outspsr = 32'hxxxxxxxx,
51 output reg [31:0] outcpsr = 32'hxxxxxxxx
a02ca509 52 );
b3bb2fb8 53
efd1aa13 54 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
e08b748a 55 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 56 reg next_writeback;
74d3729c 57 reg [31:0] align_s1, align_s2, align_rddata;
e08b748a 58
c65110a8 59 wire next_outbubble;
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60 wire next_write_reg;
61 wire [3:0] next_write_num;
62 wire [31:0] next_write_data;
74d3729c 63
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64 reg [1:0] lsr_state = 2'b01, next_lsr_state;
65
b783a475 66 reg [15:0] regs, next_regs;
9a0d0e43 67 reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f 68 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 69
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70 reg [31:0] swp_oldval, next_swp_oldval;
71 reg [1:0] swp_state = 2'b01, next_swp_state;
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72
73 always @(posedge clk)
74 begin
75 outpc <= pc;
76 outinsn <= insn;
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77 outbubble <= next_outbubble;
78 out_write_reg <= next_write_reg;
79 out_write_num <= next_write_num;
80 out_write_data <= next_write_data;
e68b2378 81 regs <= next_regs;
e08b748a 82 prev_reg <= cur_reg;
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83 prev_offset <= offset;
84 prev_raddr <= raddr;
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85 outcpsr <= next_outcpsr;
86 outspsr <= spsr;
9a0d0e43 87 swp_state <= next_swp_state;
a02ca509 88 end
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89
90 always @(*)
91 begin
92 addr = 32'hxxxxxxxx;
93 raddr = 32'hxxxxxxxx;
94 rd_req = 1'b0;
95 wr_req = 1'b0;
96 wr_data = 32'hxxxxxxxx;
97 busaddr = 32'hxxxxxxxx;
98 outstall = 1'b0;
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99 next_write_reg = write_reg;
100 next_write_num = write_num;
101 next_write_data = write_data;
c65110a8 102 next_outbubble = inbubble;
a02ca509 103 outstall = 1'b0;
9a0d0e43 104 next_regs = regs;
979f2bd7 105 cp_req = 1'b0;
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106 cp_rnw = 1'bx;
107 cp_write = 32'hxxxxxxxx;
b114e03f 108 offset = prev_offset;
ab7ee9fc 109 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
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110 next_lsm_state = lsm_state;
111 next_lsr_state = lsr_state;
112 next_swp_oldval = swp_oldval;
113 next_swp_state = swp_state;
114 cur_reg = prev_reg;
9f082c0b 115
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116 /* XXX shit not given about endianness */
117 /* TODO ldrh/strh */
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118 if (flush)
119 next_outbubble = 1'b1;
120 else casez(insn)
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121 `DECODE_ALU_SWP: if(!inbubble) begin
122 outstall = rw_wait;
123 next_outbubble = rw_wait;
124 busaddr = {op0[31:2], 2'b0};
125 case(swp_state)
126 2'b01: begin
127 rd_req = 1'b1;
128 outstall = 1'b1;
129 if(!rw_wait) begin
130 next_swp_state = 2'b10;
131 next_swp_oldval = rd_data;
9a0d0e43 132 end
9a0d0e43 133 end
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134 2'b10: begin
135 wr_req = 1'b1;
136 wr_data = op1;
137 next_write_reg = 1'b1;
138 next_write_num = insn[15:12];
139 next_write_data = swp_oldval;
140 if(!rw_wait)
141 next_swp_state = 2'b01;
142 end
143 default: begin end
144 endcase
9a0d0e43 145 end
b3bb2fb8 146 `DECODE_LDRSTR_UNDEFINED: begin end
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147 `DECODE_LDRSTR: if(!inbubble) begin
148 next_outbubble = rw_wait;
149 outstall = rw_wait;
150 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
151 raddr = insn[24] ? op0 : addr; /* pre/post increment */
152 busaddr = {raddr[31:2], 2'b0};
a02ca509 153 /* rotate to correct position */
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154 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
155 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
156 /* select byte or word */
157 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
158 if(!insn[20]) begin
159 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
160 end
161 case(lsr_state)
162 2'b01: begin
163 rd_req = insn[20];
164 wr_req = ~insn[20];
165 if(insn[20]) begin
166 next_write_reg = 1'b1;
167 next_write_num = insn[15:12];
168 next_write_data = align_rddata;
a02ca509 169 end
9a0d0e43 170 if(insn[21]) begin
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171 outstall = 1'b1;
172 if(!rw_wait)
173 next_lsr_state = 2'b10;
a02ca509 174 end
b3bb2fb8 175 end
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176 2'b10: begin
177 next_write_reg = 1'b1;
178 next_write_num = insn[19:16];
179 next_write_data = addr;
180 next_lsr_state = 2'b10;
181 end
182 default: begin end
183 endcase
b3bb2fb8 184 end
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185 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
186 `DECODE_LDMSTM: if(!inbubble) begin
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187 outstall = rw_wait;
188 next_outbubble = rw_wait;
189 case(lsm_state)
190 3'b001: begin
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191// next_regs = insn[23] ? op1[15:0] : op1[0:15];
192 /** verilator can suck my dick */
193 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
194 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
195 offset = 6'b0;
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196 outstall = 1'b1;
197 next_lsm_state = 3'b010;
e08b748a 198 end
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199 3'b010: begin
200 rd_req = insn[20];
201 wr_req = ~insn[20];
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202 casez(regs)
203 16'b???????????????1: begin
e08b748a 204 cur_reg = 4'h0;
b114e03f 205 next_regs = {regs[15:1], 1'b0};
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206 end
207 16'b??????????????10: begin
e08b748a 208 cur_reg = 4'h1;
b114e03f 209 next_regs = {regs[15:2], 2'b0};
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210 end
211 16'b?????????????100: begin
e08b748a 212 cur_reg = 4'h2;
b114e03f 213 next_regs = {regs[15:3], 3'b0};
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214 end
215 16'b????????????1000: begin
e08b748a 216 cur_reg = 4'h3;
b114e03f 217 next_regs = {regs[15:4], 4'b0};
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218 end
219 16'b???????????10000: begin
e08b748a 220 cur_reg = 4'h4;
b114e03f 221 next_regs = {regs[15:5], 5'b0};
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222 end
223 16'b??????????100000: begin
e08b748a 224 cur_reg = 4'h5;
b114e03f 225 next_regs = {regs[15:6], 6'b0};
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226 end
227 16'b?????????1000000: begin
e08b748a 228 cur_reg = 4'h6;
b114e03f 229 next_regs = {regs[15:7], 7'b0};
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230 end
231 16'b????????10000000: begin
e08b748a 232 cur_reg = 4'h7;
b114e03f 233 next_regs = {regs[15:8], 8'b0};
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234 end
235 16'b???????100000000: begin
e08b748a 236 cur_reg = 4'h8;
b114e03f 237 next_regs = {regs[15:9], 9'b0};
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238 end
239 16'b??????1000000000: begin
e08b748a 240 cur_reg = 4'h9;
b114e03f 241 next_regs = {regs[15:10], 10'b0};
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242 end
243 16'b?????10000000000: begin
e08b748a 244 cur_reg = 4'hA;
b114e03f 245 next_regs = {regs[15:11], 11'b0};
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246 end
247 16'b????100000000000: begin
e08b748a 248 cur_reg = 4'hB;
b114e03f 249 next_regs = {regs[15:12], 12'b0};
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250 end
251 16'b???1000000000000: begin
e08b748a 252 cur_reg = 4'hC;
b114e03f 253 next_regs = {regs[15:13], 13'b0};
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254 end
255 16'b??10000000000000: begin
e08b748a 256 cur_reg = 4'hD;
b114e03f 257 next_regs = {regs[15:14], 14'b0};
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258 end
259 16'b?100000000000000: begin
e08b748a 260 cur_reg = 4'hE;
b114e03f 261 next_regs = {regs[15], 15'b0};
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262 end
263 16'b1000000000000000: begin
e08b748a 264 cur_reg = 4'hF;
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265 next_regs = 16'b0;
266 end
267 default: begin
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268 cur_reg = 4'hx;
269 next_regs = 16'b0;
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270 end
271 endcase
b114e03f 272 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
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273 if(cur_reg == 4'hF && insn[22]) begin
274 next_outcpsr = spsr;
275 end
b114e03f 276
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277 if(rw_wait) begin
278 next_regs = regs;
279 cur_reg = prev_reg;
280 raddr = prev_raddr;
281 end
282 else begin
283 offset = prev_offset + 6'h4;
284 offset_sel = insn[24] ? offset : prev_offset;
285 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
286 if(insn[20]) begin
287 next_write_reg = 1'b1;
288 next_write_num = cur_reg;
289 next_write_data = rd_data;
290 end
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291 end
292
293 st_read = cur_reg;
294 wr_data = st_data;
b114e03f 295 busaddr = {raddr[31:2], 2'b0};
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296
297 outstall = 1'b1;
298
299 if(next_regs == 16'b0) begin
300 next_lsm_state = 3'b100;
301 end
302 end
303 3'b100: begin
304 next_write_reg = 1'b1;
305 next_write_num = insn[19:16];
306 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
307 next_lsm_state = 3'b001;
b783a475 308 end
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309 default: begin end
310 endcase
b3bb2fb8 311 end
5989b2f5 312 `DECODE_LDCSTC: if(!inbubble) begin
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313 $display("WARNING: Unimplemented LDCSTC");
314 end
5989b2f5 315 `DECODE_CDP: if(!inbubble) begin
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316 cp_req = 1;
317 if (cp_busy) begin
318 outstall = 1;
319 next_outbubble = 1;
320 end
321 if (!cp_ack) begin
322 /* XXX undefined instruction trap */
323 $display("WARNING: Possible CDP undefined instruction");
324 end
325 end
5989b2f5 326 `DECODE_MRCMCR: if(!inbubble) begin
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327 cp_req = 1;
328 cp_rnw = insn[20] /* L */;
329 if (insn[20] == 0 /* store to coprocessor */)
330 cp_write = op0;
331 else begin
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JW
332 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
333 next_write_reg = 1'b1;
334 next_write_num = insn[15:12];
335 next_write_data = cp_read;
336 end else
337 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
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JW
338 end
339 if (cp_busy) begin
340 outstall = 1;
341 next_outbubble = 1;
342 end
343 if (!cp_ack) begin
838e283e 344 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 345 end
838e283e 346 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 347 end
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348 default: begin end
349 endcase
350 end
b3bb2fb8 351endmodule
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