System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg [7:0] odata;
  10
  11         // synthesis attribute ram_style of rom is block
  12         reg [7:0] rom [1023:0];
  13         initial $readmemh("rom.hex", rom);
  14
  15         wire decode = address[15:13] == 0;
  16         always @(posedge clk)
  17                 odata <= rom[address[10:0]];
  18         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  19 endmodule
  20
  21 module BootstrapROM(
  22         input [15:0] address,
  23         inout [7:0] data,
  24         input clk,
  25         input wr, rd);
  26
  27         reg [7:0] brom [255:0];
  28         initial $readmemh("bootstrap.hex", brom);
  29
  30         wire decode = address[15:8] == 0;
  31         wire [7:0] odata = brom[address[7:0]];
  32         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  33 endmodule
  34
  35 module MiniRAM(
  36         input [15:0] address,
  37         inout [7:0] data,
  38         input clk,
  39         input wr, rd);
  40
  41         reg [7:0] ram [127:0];
  42
  43         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  44         reg [7:0] odata;
  45         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  46
  47         always @(posedge clk)
  48         begin
  49                 if (decode)     // This has to go this way. The only way XST knows how to do
  50                 begin                           // block ram is chip select, write enable, and always
  51                         if (wr)         // reading. "else if rd" does not cut it ...
  52                                 ram[address[6:0]] <= data;
  53                         odata <= ram[address[6:0]];
  54                 end
  55         end
  56 endmodule
  57
  58 module InternalRAM(
  59         input [15:0] address,
  60         inout [7:0] data,
  61         input clk,
  62         input wr, rd);
  63
  64         // synthesis attribute ram_style of ram is block
  65         reg [7:0] ram [8191:0];
  66
  67         wire decode = address[15:13] == 3'b110;
  68         reg [7:0] odata;
  69         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  70
  71         always @(posedge clk)
  72         begin
  73                 if (decode)     // This has to go this way. The only way XST knows how to do
  74                 begin                           // block ram is chip select, write enable, and always
  75                         if (wr)         // reading. "else if rd" does not cut it ...
  76                                 ram[address[12:0]] <= data;
  77                         odata <= ram[address[12:0]];
  78                 end
  79         end
  80 endmodule
  81
  82 module Switches(
  83         input [15:0] address,
  84         inout [7:0] data,
  85         input clk,
  86         input wr, rd,
  87         input [7:0] switches,
  88         output reg [7:0] ledout = 0);
  89
  90         wire decode = address == 16'hFF51;
  91         reg [7:0] odata;
  92         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  93
  94         always @(posedge clk)
  95         begin
  96                 if (decode && rd)
  97                         odata <= switches;
  98                 else if (decode && wr)
  99                         ledout <= data;
 100         end
 101 endmodule
 102
 103 `ifdef isim
 104 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
 105 endmodule
 106 `endif
 107
 108 module CoreTop(
 109 `ifdef isim
 110         output reg vgaclk = 0,
 111         output reg clk = 0,
 112 `else
 113         input xtal,
 114         input [7:0] switches,
 115         input [3:0] buttons,
 116         output wire [7:0] leds,
 117         output serio,
 118         output wire [3:0] digits,
 119         output wire [7:0] seven,
 120 `endif
 121         output wire hs, vs,
 122         output wire [2:0] r, g,
 123         output wire [1:0] b,
 124         output wire soundl, soundr);
 125
 126 `ifdef isim
 127         always #62 clk <= ~clk;
 128         always #100 vgaclk <= ~vgaclk;
 129
 130         Dumpable dump(r,g,b,hs,vs,vgaclk);
 131
 132         wire [7:0] leds;
 133         wire serio;
 134         wire [3:0] digits;
 135         wire [7:0] seven;
 136         wire [7:0] switches = 8'b0;
 137         wire [3:0] buttons = 4'b0;
 138 `else
 139         wire xtalb, clk, vgaclk;
 140         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 141         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 142         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 143 `endif
 144
 145         wire [15:0] addr [1:0];
 146         wire [7:0] data [1:0];
 147         wire wr [1:0], rd [1:0];
 148
 149         wire irq, tmrirq, lcdcirq, vblankirq;
 150         wire [7:0] jaddr;
 151         wire [1:0] state;
 152
 153         GBZ80Core core(
 154                 .clk(clk),
 155                 .bus0address(addr[0]),
 156                 .bus0data(data[0]),
 157                 .bus0wr(wr[0]),
 158                 .bus0rd(rd[0]),
 159                 .bus1address(addr[1]),
 160                 .bus1data(data[1]),
 161                 .bus1wr(wr[1]),
 162                 .bus1rd(rd[1]),
 163                 .irq(irq),
 164                 .jaddr(jaddr),
 165                 .state(state));
 166
 167         BootstrapROM brom(
 168                 .address(addr[1]),
 169                 .data(data[1]),
 170                 .clk(clk),
 171                 .wr(wr[1]),
 172                 .rd(rd[1]));
 173
 174         ROM rom(
 175                 .address(addr[0]),
 176                 .data(data[0]),
 177                 .clk(clk),
 178                 .wr(wr[0]),
 179                 .rd(rd[0]));
 180
 181         wire lcdhs, lcdvs, lcdclk;
 182         wire [2:0] lcdr, lcdg;
 183         wire [1:0] lcdb;
 184
 185         LCDC lcdc(
 186                 .clk(clk),
 187                 .addr(addr[0]),
 188                 .data(data[0]),
 189                 .wr(wr[0]),
 190                 .rd(rd[0]),
 191                 .lcdcirq(lcdcirq),
 192                 .vblankirq(vblankirq),
 193                 .lcdclk(lcdclk),
 194                 .lcdhs(lcdhs),
 195                 .lcdvs(lcdvs),
 196                 .lcdr(lcdr),
 197                 .lcdg(lcdg),
 198                 .lcdb(lcdb));
 199
 200         Framebuffer fb(
 201                 .lcdclk(lcdclk),
 202                 .lcdhs(lcdhs),
 203                 .lcdvs(lcdvs),
 204                 .lcdr(lcdr),
 205                 .lcdg(lcdg),
 206                 .lcdb(lcdb),
 207                 .vgaclk(vgaclk),
 208                 .vgahs(hs),
 209                 .vgavs(vs),
 210                 .vgar(r),
 211                 .vgag(g),
 212                 .vgab(b));
 213
 214         AddrMon amon(
 215                 .clk(clk),
 216                 .addr(addr[0]),
 217                 .digit(digits),
 218                 .out(seven),
 219                 .freeze(buttons[0]),
 220                 .periods(
 221                         (state == 2'b00) ? 4'b0010 :
 222                         (state == 2'b01) ? 4'b0001 :
 223                         (state == 2'b10) ? 4'b1000 :
 224                                            4'b0100) );
 225
 226         Switches sw(
 227                 .clk(clk),
 228                 .address(addr[0]),
 229                 .data(data[0]),
 230                 .wr(wr[0]),
 231                 .rd(rd[0]),
 232                 .ledout(leds),
 233                 .switches(switches)
 234                 );
 235
 236         UART nouart (   /* no u */
 237                 .clk(clk),
 238                 .addr(addr[0]),
 239                 .data(data[0]),
 240                 .wr(wr[0]),
 241                 .rd(rd[0]),
 242                 .serial(serio)
 243                 );
 244
 245         InternalRAM ram(
 246                 .clk(clk),
 247                 .address(addr[0]),
 248                 .data(data[0]),
 249                 .wr(wr[0]),
 250                 .rd(rd[0])
 251                 );
 252
 253         MiniRAM mram(
 254                 .clk(clk),
 255                 .address(addr[1]),
 256                 .data(data[1]),
 257                 .wr(wr[1]),
 258                 .rd(rd[1])
 259                 );
 260
 261         Timer tmr(
 262                 .clk(clk),
 263                 .addr(addr[0]),
 264                 .data(data[0]),
 265                 .wr(wr[0]),
 266                 .rd(rd[0]),
 267                 .irq(tmrirq)
 268                 );
 269
 270         Interrupt intr(
 271                 .clk(clk),
 272                 .addr(addr[0]),
 273                 .data(data[0]),
 274                 .wr(wr[0]),
 275                 .rd(rd[0]),
 276                 .vblank(vblankirq),
 277                 .lcdc(lcdcirq),
 278                 .tovf(tmrirq),
 279                 .serial(1'b0),
 280                 .buttons(1'b0),
 281                 .master(irq),
 282                 .jaddr(jaddr));
 283
 284         Soundcore sound(
 285                 .core_clk(clk),
 286                 .addr(addr[0]),
 287                 .data(data[0]),
 288                 .rd(rd[0]),
 289                 .wr(wr[0]),
 290                 .snd_data_l(soundl),
 291                 .snd_data_r(soundr));
 292 endmodule