[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg [7:0] rom [1023:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	wire [7:0] odata = rom[address[10:0]];
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	//assign data = rd ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(			/* XXX will need to go INSIDE the CPU for when we do DMA */
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(negedge clk)
	begin
		if (decode)	// This has to go this way. The only way XST knows how to do
		begin				// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = address[15:13] == 3'b110;
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(negedge clk)
	begin
		if (decode)	// This has to go this way. The only way XST knows how to do
		begin				// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(negedge clk)
	begin
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	output wire [3:0] digits,
	output wire [7:0] seven,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr;	
	wire [7:0] data;
	wire wr, rd;
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	
	GBZ80Core core(
		.clk(clk),
		.busaddress(addr),
		.busdata(data),
		.buswr(wr),
		.busrd(rd),
		.irq(irq),
		.jaddr(jaddr),
		.state(state));
	
	ROM rom(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd));
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.addr(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));
	
	AddrMon amon(
		.addr(addr), 
		.clk(clk), 
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	Switches sw(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (	/* no u */
		.clk(clk), 
		.wr(wr), 
		.rd(rd), 
		.addr(addr), 
		.data(data), 
		.serial(serio)
		);

	InternalRAM ram(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd)
		);
	
	MiniRAM mram(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd)
		);

	Timer tmr(
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.addr(addr),
		.data(data),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.rd(rd),
		.wr(wr),
		.addr(addr),
		.data(data),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.rd(rd),
		.wr(wr),
		.addr(addr),
		.data(data),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule

`ifdef verilator
`else
module TestBench();
	reg clk = 1;
	wire [15:0] addr;
	wire [7:0] data;
	wire wr, rd;
	
	wire irq, tmrirq;
	wire [7:0] jaddr;
	
	wire [7:0] leds;
	wire [7:0] switches;
	
	always #62 clk <= ~clk;
	GBZ80Core core(
		.clk(clk),
		.busaddress(addr),
		.busdata(data),
		.buswr(wr),
		.busrd(rd),
		.irq(irq),
		.jaddr(jaddr));
	
	ROM rom(
		.clk(clk),
		.address(addr),
		.data(data),
		.wr(wr),
		.rd(rd));
	
	InternalRAM ram(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd));

	wire serio;
	UART uart(
		.addr(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.serial(serio));
	
	Timer tmr(
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.addr(addr),
		.data(data),
		.irq(tmrirq));
	
	Interrupt intr(
		.clk(clk),
		.rd(rd),
		.wr(wr),
		.addr(addr),
		.data(data),
		.vblank(0),
		.lcdc(0),
		.tovf(tmrirq),
		.serial(0),
		.buttons(0),
		.master(irq),
		.jaddr(jaddr));
	
	Switches sw(
		.clk(clk),
		.address(addr),
		.data(data),
		.wr(wr),
		.rd(rd),
		.switches(switches),
		.ledout(leds));
endmodule
`endif
Commit	Line	Data
a85b19a7 JW	1
	2	`timescale 1ns / 1ps
	3	module ROM(
	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
fe3dc890	9	reg [7:0] rom [1023:0];
a85b19a7 JW	10	initial $readmemh("rom.hex", rom);
	11
	12	wire decode = address[15:13] == 0;
fe3dc890	13	wire [7:0] odata = rom[address[10:0]];
a85b19a7 JW	14	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	15	//assign data = rd ? odata : 8'bzzzzzzzz;
	16	endmodule
	17
6bd4619b JW	18	module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */
	19	input [15:0] address,
	20	inout [7:0] data,
	21	input clk,
	22	input wr, rd);
	23
	24	reg [7:0] ram [127:0];
	25
	26	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	27	reg [7:0] odata;
	28	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	29
	30	always @(negedge clk)
	31	begin
	32	if (decode) // This has to go this way. The only way XST knows how to do
	33	begin // block ram is chip select, write enable, and always
	34	if (wr) // reading. "else if rd" does not cut it ...
	35	ram[address[6:0]] <= data;
	36	odata <= ram[address[6:0]];
	37	end
	38	end
c279b666	39	endmodule
6bd4619b	40
a85b19a7 JW	41	module InternalRAM(
	42	input [15:0] address,
	43	inout [7:0] data,
	44	input clk,
	45	input wr, rd);
	46
fe3dc890	47	// synthesis attribute ram_style of ram is block
616eebe0	48	reg [7:0] ram [8191:0];
a85b19a7	49
c87db60a	50	wire decode = address[15:13] == 3'b110;
a85b19a7	51	reg [7:0] odata;
a85b19a7 JW	52	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	53
	54	always @(negedge clk)
	55	begin
95143d64 JW	56	if (decode) // This has to go this way. The only way XST knows how to do
	57	begin // block ram is chip select, write enable, and always
	58	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	59	ram[address[12:0]] <= data;
616eebe0 JW	60	odata <= ram[address[12:0]];
c87db60a	61	end
a85b19a7 JW	62	end
	63	endmodule
	64
	65	module Switches(
	66	input [15:0] address,
	67	inout [7:0] data,
	68	input clk,
	69	input wr, rd,
	70	input [7:0] switches,
9c834ff2	71	output reg [7:0] ledout = 0);
a85b19a7 JW	72
	73	wire decode = address == 16'hFF51;
	74	reg [7:0] odata;
	75	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	76
	77	always @(negedge clk)
	78	begin
	79	if (decode && rd)
	80	odata <= switches;
	81	else if (decode && wr)
	82	ledout <= data;
	83	end
	84	endmodule
	85
e7fb589a JW	86	`ifdef isim
	87	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	88	endmodule
	89	`endif
	90
a85b19a7	91	module CoreTop(
e7fb589a JW	92	`ifdef isim
	93	output reg vgaclk = 0,
	94	output reg clk = 0,
	95	`else
a85b19a7 JW	96	input xtal,
a85b19a7 JW	97	input [7:0] switches,
ff7fd7f2	98	input [3:0] buttons,
a85b19a7 JW	99	output wire [7:0] leds,
	100	output serio,
	101	output wire [3:0] digits,
00573fd5	102	output wire [7:0] seven,
e7fb589a	103	`endif
00573fd5 JW	104	output wire hs, vs,
00573fd5 JW	105	output wire [2:0] r, g,
09c1936c JW	106	output wire [1:0] b,
09c1936c JW	107	output wire soundl, soundr);
e7fb589a JW	108
	109	`ifdef isim
	110	always #62 clk <= ~clk;
	111	always #100 vgaclk <= ~vgaclk;
	112
	113	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	114
e7fb589a JW	115	wire [7:0] leds;
	116	wire serio;
	117	wire [3:0] digits;
	118	wire [7:0] seven;
	119	wire [7:0] switches = 8'b0;
	120	wire [3:0] buttons = 4'b0;
	121	`else
fe3dc890 JW	122	wire xtalb, clk, vgaclk;
	123	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	124	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	125	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	126	`endif
e7fb589a JW	127
a85b19a7 JW	128	wire [15:0] addr;
	129	wire [7:0] data;
	130	wire wr, rd;
f8db6448	131
00573fd5	132	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	133	wire [7:0] jaddr;
6c46357c	134	wire [1:0] state;
179b4347	135
a85b19a7	136	GBZ80Core core(
179b4347	137	.clk(clk),
a85b19a7 JW	138	.busaddress(addr),
	139	.busdata(data),
	140	.buswr(wr),
f8db6448 JW	141	.busrd(rd),
f8db6448 JW	142	.irq(irq),
6c46357c JW	143	.jaddr(jaddr),
6c46357c JW	144	.state(state));
a85b19a7 JW	145
	146	ROM rom(
	147	.address(addr),
	148	.data(data),
	149	.clk(clk),
	150	.wr(wr),
	151	.rd(rd));
	152
fe3dc890 JW	153	wire lcdhs, lcdvs, lcdclk;
	154	wire [2:0] lcdr, lcdg;
	155	wire [1:0] lcdb;
	156
537e1f83 JW	157	LCDC lcdc(
	158	.addr(addr),
	159	.data(data),
	160	.clk(clk),
	161	.wr(wr),
	162	.rd(rd),
00573fd5 JW	163	.lcdcirq(lcdcirq),
00573fd5 JW	164	.vblankirq(vblankirq),
fe3dc890 JW	165	.lcdclk(lcdclk),
	166	.lcdhs(lcdhs),
	167	.lcdvs(lcdvs),
	168	.lcdr(lcdr),
	169	.lcdg(lcdg),
	170	.lcdb(lcdb));
	171
	172	Framebuffer fb(
	173	.lcdclk(lcdclk),
	174	.lcdhs(lcdhs),
	175	.lcdvs(lcdvs),
	176	.lcdr(lcdr),
	177	.lcdg(lcdg),
	178	.lcdb(lcdb),
	179	.vgaclk(vgaclk),
00573fd5 JW	180	.vgahs(hs),
	181	.vgavs(vs),
	182	.vgar(r),
	183	.vgag(g),
	184	.vgab(b));
537e1f83	185
a85b19a7	186	AddrMon amon(
eb0f2fe1 JW	187	.addr(addr),
	188	.clk(clk),
	189	.digit(digits),
	190	.out(seven),
6c46357c JW	191	.freeze(buttons[0]),
6c46357c JW	192	.periods(
179b4347 JW	193	(state == 2'b00) ? 4'b0010 :
	194	(state == 2'b01) ? 4'b0001 :
	195	(state == 2'b10) ? 4'b1000 :
	196	4'b0100) );
a85b19a7 JW	197
	198	Switches sw(
	199	.address(addr),
	200	.data(data),
	201	.clk(clk),
	202	.wr(wr),
	203	.rd(rd),
	204	.ledout(leds),
fc443a4f	205	.switches(switches)
a85b19a7 JW	206	);
a85b19a7 JW	207
06ad3a30	208	UART nouart ( /* no u */
eb0f2fe1 JW	209	.clk(clk),
	210	.wr(wr),
	211	.rd(rd),
	212	.addr(addr),
	213	.data(data),
	214	.serial(serio)
	215	);
9aa931d1	216
eb0f2fe1	217	InternalRAM ram(
9aa931d1 JW	218	.address(addr),
	219	.data(data),
	220	.clk(clk),
	221	.wr(wr),
eb0f2fe1 JW	222	.rd(rd)
eb0f2fe1 JW	223	);
6bd4619b JW	224
	225	MiniRAM mram(
	226	.address(addr),
	227	.data(data),
	228	.clk(clk),
	229	.wr(wr),
	230	.rd(rd)
	231	);
06ad3a30	232
06ad3a30 JW	233	Timer tmr(
	234	.clk(clk),
	235	.wr(wr),
	236	.rd(rd),
	237	.addr(addr),
	238	.data(data),
eb0f2fe1 JW	239	.irq(tmrirq)
eb0f2fe1 JW	240	);
06ad3a30 JW	241
	242	Interrupt intr(
	243	.clk(clk),
	244	.rd(rd),
	245	.wr(wr),
	246	.addr(addr),
	247	.data(data),
00573fd5	248	.vblank(vblankirq),
537e1f83	249	.lcdc(lcdcirq),
06ad3a30	250	.tovf(tmrirq),
e7fb589a JW	251	.serial(1'b0),
e7fb589a JW	252	.buttons(1'b0),
06ad3a30 JW	253	.master(irq),
06ad3a30 JW	254	.jaddr(jaddr));
09c1936c JW	255
	256	Soundcore sound(
	257	.core_clk(clk),
	258	.rd(rd),
	259	.wr(wr),
	260	.addr(addr),
	261	.data(data),
	262	.snd_data_l(soundl),
	263	.snd_data_r(soundr));
a85b19a7 JW	264	endmodule
a85b19a7 JW	265
e7fb589a JW	266	`ifdef verilator
e7fb589a JW	267	`else
a85b19a7	268	module TestBench();
62940da0	269	reg clk = 1;
a85b19a7 JW	270	wire [15:0] addr;
	271	wire [7:0] data;
	272	wire wr, rd;
	273
f8db6448 JW	274	wire irq, tmrirq;
	275	wire [7:0] jaddr;
	276
9c834ff2 JW	277	wire [7:0] leds;
9c834ff2 JW	278	wire [7:0] switches;
a85b19a7	279
179b4347	280	always #62 clk <= ~clk;
a85b19a7 JW	281	GBZ80Core core(
	282	.clk(clk),
	283	.busaddress(addr),
	284	.busdata(data),
	285	.buswr(wr),
f8db6448 JW	286	.busrd(rd),
	287	.irq(irq),
	288	.jaddr(jaddr));
a85b19a7 JW	289
	290	ROM rom(
	291	.clk(clk),
	292	.address(addr),
	293	.data(data),
	294	.wr(wr),
	295	.rd(rd));
	296
9aa931d1 JW	297	InternalRAM ram(
	298	.address(addr),
	299	.data(data),
	300	.clk(clk),
	301	.wr(wr),
	302	.rd(rd));
a85b19a7	303
6493be2b JW	304	wire serio;
	305	UART uart(
	306	.addr(addr),
	307	.data(data),
	308	.clk(clk),
	309	.wr(wr),
	310	.rd(rd),
	311	.serial(serio));
a85b19a7	312
06ad3a30 JW	313	Timer tmr(
	314	.clk(clk),
	315	.wr(wr),
	316	.rd(rd),
	317	.addr(addr),
	318	.data(data),
	319	.irq(tmrirq));
	320
	321	Interrupt intr(
	322	.clk(clk),
	323	.rd(rd),
	324	.wr(wr),
	325	.addr(addr),
	326	.data(data),
	327	.vblank(0),
	328	.lcdc(0),
	329	.tovf(tmrirq),
	330	.serial(0),
	331	.buttons(0),
	332	.master(irq),
	333	.jaddr(jaddr));
	334
9c834ff2 JW	335	Switches sw(
	336	.clk(clk),
	337	.address(addr),
	338	.data(data),
	339	.wr(wr),
	340	.rd(rd),
	341	.switches(switches),
	342	.ledout(leds));
a85b19a7	343	endmodule
e7fb589a	344	`endif