First cut at timer
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
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28 reg [7:0] odata;
29 wire idata = data;
30 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
31
32 always @(negedge clk)
33 begin
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34 if (decode) // This has to go this way. The only way XST knows how to do
35 begin // block ram is chip select, write enable, and always
36 if (wr) // reading. "else if rd" does not cut it ...
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37 ram[address[12:0]] <= data;
38 odata <= ram[address[12:0]];
c87db60a 39 end
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40 end
41endmodule
42
43module Switches(
44 input [15:0] address,
45 inout [7:0] data,
46 input clk,
47 input wr, rd,
48 input [7:0] switches,
49 output reg [7:0] ledout);
50
51 wire decode = address == 16'hFF51;
52 reg [7:0] odata;
53 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
54
55 always @(negedge clk)
56 begin
57 if (decode && rd)
58 odata <= switches;
59 else if (decode && wr)
60 ledout <= data;
61 end
62endmodule
63
64module CoreTop(
65 input xtal,
66 input [7:0] switches,
ff7fd7f2 67 input [3:0] buttons,
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68 output wire [7:0] leds,
69 output serio,
70 output wire [3:0] digits,
71 output wire [7:0] seven);
72
06ad3a30 73 wire clk;
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74 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
75
76 wire [15:0] addr;
77 wire [7:0] data;
78 wire wr, rd;
79
80 GBZ80Core core(
81 .clk(clk),
82 .busaddress(addr),
83 .busdata(data),
84 .buswr(wr),
85 .busrd(rd));
86
87 ROM rom(
88 .address(addr),
89 .data(data),
90 .clk(clk),
91 .wr(wr),
92 .rd(rd));
93
94 AddrMon amon(
95 .addr(addr),
96 .clk(clk),
97 .digit(digits),
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98 .out(seven),
99 .freeze(buttons[0])
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100 );
101
102 Switches sw(
103 .address(addr),
104 .data(data),
105 .clk(clk),
106 .wr(wr),
107 .rd(rd),
108 .ledout(leds),
109 .switches(switches)
110 );
111
06ad3a30 112 UART nouart ( /* no u */
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113 .clk(clk),
114 .wr(wr),
115 .rd(rd),
116 .addr(addr),
117 .data(data),
118 .serial(serio)
119 );
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120
121 InternalRAM ram(
122 .address(addr),
123 .data(data),
124 .clk(clk),
125 .wr(wr),
126 .rd(rd));
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127
128 wire irq, tmrirq;
129 wire [7:0] jaddr;
130 Timer tmr(
131 .clk(clk),
132 .wr(wr),
133 .rd(rd),
134 .addr(addr),
135 .data(data),
136 .irq(tmrirq));
137
138 Interrupt intr(
139 .clk(clk),
140 .rd(rd),
141 .wr(wr),
142 .addr(addr),
143 .data(data),
144 .vblank(0),
145 .lcdc(0),
146 .tovf(tmrirq),
147 .serial(0),
148 .buttons(0),
149 .master(irq),
150 .jaddr(jaddr));
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151endmodule
152
153module TestBench();
154 reg clk = 0;
155 wire [15:0] addr;
156 wire [7:0] data;
157 wire wr, rd;
158
159// wire [7:0] leds;
160// wire [7:0] switches;
161
162 always #10 clk <= ~clk;
163 GBZ80Core core(
164 .clk(clk),
165 .busaddress(addr),
166 .busdata(data),
167 .buswr(wr),
168 .busrd(rd));
169
170 ROM rom(
171 .clk(clk),
172 .address(addr),
173 .data(data),
174 .wr(wr),
175 .rd(rd));
176
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177 InternalRAM ram(
178 .address(addr),
179 .data(data),
180 .clk(clk),
181 .wr(wr),
182 .rd(rd));
a85b19a7 183
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184 wire serio;
185 UART uart(
186 .addr(addr),
187 .data(data),
188 .clk(clk),
189 .wr(wr),
190 .rd(rd),
191 .serial(serio));
a85b19a7 192
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193 wire irq, tmrirq;
194 wire [7:0] jaddr;
195 Timer tmr(
196 .clk(clk),
197 .wr(wr),
198 .rd(rd),
199 .addr(addr),
200 .data(data),
201 .irq(tmrirq));
202
203 Interrupt intr(
204 .clk(clk),
205 .rd(rd),
206 .wr(wr),
207 .addr(addr),
208 .data(data),
209 .vblank(0),
210 .lcdc(0),
211 .tovf(tmrirq),
212 .serial(0),
213 .buttons(0),
214 .master(irq),
215 .jaddr(jaddr));
216
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217// Switches sw(
218// .clk(clk),
219// .address(addr),
220// .data(data),
221// .wr(wr),
222// .rd(rd),
223// .switches(switches),
224// .leds(leds));
225endmodule
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