Add some verilator and isim compatibility
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [1023:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[10:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module MiniRAM(                 /* XXX will need to go INSIDE the CPU for when we do DMA */
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         reg [7:0] ram [127:0];
25         
26         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27         reg [7:0] odata;
28         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29         
30         always @(negedge clk)
31         begin
32                 if (decode)     // This has to go this way. The only way XST knows how to do
33                 begin                           // block ram is chip select, write enable, and always
34                         if (wr)         // reading. "else if rd" does not cut it ...
35                                 ram[address[6:0]] <= data;
36                         odata <= ram[address[6:0]];
37                 end
38         end
39 endmodule
40
41 module InternalRAM(
42         input [15:0] address,
43         inout [7:0] data,
44         input clk,
45         input wr, rd);
46         
47         // synthesis attribute ram_style of ram is block
48         reg [7:0] ram [8191:0];
49         
50         wire decode = address[15:13] == 3'b110;
51         reg [7:0] odata;
52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53         
54         always @(negedge clk)
55         begin
56                 if (decode)     // This has to go this way. The only way XST knows how to do
57                 begin                           // block ram is chip select, write enable, and always
58                         if (wr)         // reading. "else if rd" does not cut it ...
59                                 ram[address[12:0]] <= data;
60                         odata <= ram[address[12:0]];
61                 end
62         end
63 endmodule
64
65 module Switches(
66         input [15:0] address,
67         inout [7:0] data,
68         input clk,
69         input wr, rd,
70         input [7:0] switches,
71         output reg [7:0] ledout = 0);
72         
73         wire decode = address == 16'hFF51;
74         reg [7:0] odata;
75         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
76         
77         always @(negedge clk)
78         begin
79                 if (decode && rd)
80                         odata <= switches;
81                 else if (decode && wr)
82                         ledout <= data;
83         end
84 endmodule
85
86 `ifdef isim
87 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
88 endmodule
89 `endif
90
91 module CoreTop(
92 `ifdef isim
93         output reg vgaclk = 0,
94         output reg clk = 0,
95 `else
96         input xtal,
97         input [7:0] switches,
98         input [3:0] buttons,
99         output wire [7:0] leds,
100         output serio,
101         output wire [3:0] digits,
102         output wire [7:0] seven,
103 `endif
104         output wire hs, vs,
105         output wire [2:0] r, g,
106         output wire [1:0] b,
107         output wire soundl, soundr);
108
109 `ifdef isim
110         always #62 clk <= ~clk;
111         always #100 vgaclk <= ~vgaclk;
112         
113         Dumpable dump(r,g,b,hs,vs,vgaclk);
114         
115         wire [7:0] leds;
116         wire serio;
117         wire [3:0] digits;
118         wire [7:0] seven;
119         wire [7:0] switches = 8'b0;
120         wire [3:0] buttons = 4'b0;
121 `else   
122         wire xtalb, clk, vgaclk;
123         IBUFG iclkbuf(.O(xtalb), .I(xtal));
124         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
125         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
126 `endif
127
128         wire [15:0] addr;       
129         wire [7:0] data;
130         wire wr, rd;
131         
132         wire irq, tmrirq, lcdcirq, vblankirq;
133         wire [7:0] jaddr;
134         wire [1:0] state;
135         
136         GBZ80Core core(
137                 .clk(clk),
138                 .busaddress(addr),
139                 .busdata(data),
140                 .buswr(wr),
141                 .busrd(rd),
142                 .irq(irq),
143                 .jaddr(jaddr),
144                 .state(state));
145         
146         ROM rom(
147                 .address(addr),
148                 .data(data),
149                 .clk(clk),
150                 .wr(wr),
151                 .rd(rd));
152         
153         wire lcdhs, lcdvs, lcdclk;
154         wire [2:0] lcdr, lcdg;
155         wire [1:0] lcdb;
156         
157         LCDC lcdc(
158                 .addr(addr),
159                 .data(data),
160                 .clk(clk),
161                 .wr(wr),
162                 .rd(rd),
163                 .lcdcirq(lcdcirq),
164                 .vblankirq(vblankirq),
165                 .lcdclk(lcdclk),
166                 .lcdhs(lcdhs),
167                 .lcdvs(lcdvs),
168                 .lcdr(lcdr),
169                 .lcdg(lcdg),
170                 .lcdb(lcdb));
171         
172         Framebuffer fb(
173                 .lcdclk(lcdclk),
174                 .lcdhs(lcdhs),
175                 .lcdvs(lcdvs),
176                 .lcdr(lcdr),
177                 .lcdg(lcdg),
178                 .lcdb(lcdb),
179                 .vgaclk(vgaclk),
180                 .vgahs(hs),
181                 .vgavs(vs),
182                 .vgar(r),
183                 .vgag(g),
184                 .vgab(b));
185         
186         AddrMon amon(
187                 .addr(addr), 
188                 .clk(clk), 
189                 .digit(digits), 
190                 .out(seven),
191                 .freeze(buttons[0]),
192                 .periods(
193                         (state == 2'b00) ? 4'b0010 :
194                         (state == 2'b01) ? 4'b0001 :
195                         (state == 2'b10) ? 4'b1000 :
196                                            4'b0100) );
197          
198         Switches sw(
199                 .address(addr),
200                 .data(data),
201                 .clk(clk),
202                 .wr(wr),
203                 .rd(rd),
204                 .ledout(leds),
205                 .switches(switches)
206                 );
207
208         UART nouart (   /* no u */
209                 .clk(clk), 
210                 .wr(wr), 
211                 .rd(rd), 
212                 .addr(addr), 
213                 .data(data), 
214                 .serial(serio)
215                 );
216
217         InternalRAM ram(
218                 .address(addr),
219                 .data(data),
220                 .clk(clk),
221                 .wr(wr),
222                 .rd(rd)
223                 );
224         
225         MiniRAM mram(
226                 .address(addr),
227                 .data(data),
228                 .clk(clk),
229                 .wr(wr),
230                 .rd(rd)
231                 );
232
233         Timer tmr(
234                 .clk(clk),
235                 .wr(wr),
236                 .rd(rd),
237                 .addr(addr),
238                 .data(data),
239                 .irq(tmrirq)
240                 );
241         
242         Interrupt intr(
243                 .clk(clk),
244                 .rd(rd),
245                 .wr(wr),
246                 .addr(addr),
247                 .data(data),
248                 .vblank(vblankirq),
249                 .lcdc(lcdcirq),
250                 .tovf(tmrirq),
251                 .serial(1'b0),
252                 .buttons(1'b0),
253                 .master(irq),
254                 .jaddr(jaddr));
255         
256         Soundcore sound(
257                 .core_clk(clk),
258                 .rd(rd),
259                 .wr(wr),
260                 .addr(addr),
261                 .data(data),
262                 .snd_data_l(soundl),
263                 .snd_data_r(soundr));
264 endmodule
265
266 `ifdef verilator
267 `else
268 module TestBench();
269         reg clk = 1;
270         wire [15:0] addr;
271         wire [7:0] data;
272         wire wr, rd;
273         
274         wire irq, tmrirq;
275         wire [7:0] jaddr;
276         
277         wire [7:0] leds;
278         wire [7:0] switches;
279         
280         always #62 clk <= ~clk;
281         GBZ80Core core(
282                 .clk(clk),
283                 .busaddress(addr),
284                 .busdata(data),
285                 .buswr(wr),
286                 .busrd(rd),
287                 .irq(irq),
288                 .jaddr(jaddr));
289         
290         ROM rom(
291                 .clk(clk),
292                 .address(addr),
293                 .data(data),
294                 .wr(wr),
295                 .rd(rd));
296         
297         InternalRAM ram(
298                 .address(addr),
299                 .data(data),
300                 .clk(clk),
301                 .wr(wr),
302                 .rd(rd));
303
304         wire serio;
305         UART uart(
306                 .addr(addr),
307                 .data(data),
308                 .clk(clk),
309                 .wr(wr),
310                 .rd(rd),
311                 .serial(serio));
312         
313         Timer tmr(
314                 .clk(clk),
315                 .wr(wr),
316                 .rd(rd),
317                 .addr(addr),
318                 .data(data),
319                 .irq(tmrirq));
320         
321         Interrupt intr(
322                 .clk(clk),
323                 .rd(rd),
324                 .wr(wr),
325                 .addr(addr),
326                 .data(data),
327                 .vblank(0),
328                 .lcdc(0),
329                 .tovf(tmrirq),
330                 .serial(0),
331                 .buttons(0),
332                 .master(irq),
333                 .jaddr(jaddr));
334         
335         Switches sw(
336                 .clk(clk),
337                 .address(addr),
338                 .data(data),
339                 .wr(wr),
340                 .rd(rd),
341                 .switches(switches),
342                 .ledout(leds));
343 endmodule
344 `endif
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