System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         // synthesis attribute ram_style of rom is block
  10         reg [7:0] rom [1023:0];
  11         initial $readmemh("rom.hex", rom);
  12
  13         wire decode = address[15:13] == 0;
  14         wire [7:0] odata = rom[address[10:0]];
  15         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  16 endmodule
  17
  18 module BootstrapROM(
  19         input [15:0] address,
  20         inout [7:0] data,
  21         input clk,
  22         input wr, rd);
  23
  24         reg [7:0] rom [255:0];
  25         initial $readmemh("bootstrap.hex", rom);
  26
  27         wire decode = address[15:8] == 0;
  28         wire [7:0] odata = rom[address[7:0]];
  29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  30 endmodule
  31
  32 module MiniRAM(
  33         input [15:0] address,
  34         inout [7:0] data,
  35         input clk,
  36         input wr, rd);
  37
  38         reg [7:0] ram [127:0];
  39
  40         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  41         reg [7:0] odata;
  42         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  43
  44         always @(posedge clk)
  45         begin
  46                 if (decode)     // This has to go this way. The only way XST knows how to do
  47                 begin                           // block ram is chip select, write enable, and always
  48                         if (wr)         // reading. "else if rd" does not cut it ...
  49                                 ram[address[6:0]] <= data;
  50                         odata <= ram[address[6:0]];
  51                 end
  52         end
  53 endmodule
  54
  55 module InternalRAM(
  56         input [15:0] address,
  57         inout [7:0] data,
  58         input clk,
  59         input wr, rd);
  60
  61         // synthesis attribute ram_style of ram is block
  62         reg [7:0] ram [8191:0];
  63
  64         wire decode = address[15:13] == 3'b110;
  65         reg [7:0] odata;
  66         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  67
  68         always @(posedge clk)
  69         begin
  70                 if (decode)     // This has to go this way. The only way XST knows how to do
  71                 begin                           // block ram is chip select, write enable, and always
  72                         if (wr)         // reading. "else if rd" does not cut it ...
  73                                 ram[address[12:0]] <= data;
  74                         odata <= ram[address[12:0]];
  75                 end
  76         end
  77 endmodule
  78
  79 module Switches(
  80         input [15:0] address,
  81         inout [7:0] data,
  82         input clk,
  83         input wr, rd,
  84         input [7:0] switches,
  85         output reg [7:0] ledout = 0);
  86
  87         wire decode = address == 16'hFF51;
  88         reg [7:0] odata;
  89         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  90
  91         always @(posedge clk)
  92         begin
  93                 if (decode && rd)
  94                         odata <= switches;
  95                 else if (decode && wr)
  96                         ledout <= data;
  97         end
  98 endmodule
  99
 100 `ifdef isim
 101 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
 102 endmodule
 103 `endif
 104
 105 module CoreTop(
 106 `ifdef isim
 107         output reg vgaclk = 0,
 108         output reg clk = 0,
 109 `else
 110         input xtal,
 111         input [7:0] switches,
 112         input [3:0] buttons,
 113         output wire [7:0] leds,
 114         output serio,
 115         output wire [3:0] digits,
 116         output wire [7:0] seven,
 117 `endif
 118         output wire hs, vs,
 119         output wire [2:0] r, g,
 120         output wire [1:0] b,
 121         output wire soundl, soundr);
 122
 123 `ifdef isim
 124         always #62 clk <= ~clk;
 125         always #100 vgaclk <= ~vgaclk;
 126
 127         Dumpable dump(r,g,b,hs,vs,vgaclk);
 128
 129         wire [7:0] leds;
 130         wire serio;
 131         wire [3:0] digits;
 132         wire [7:0] seven;
 133         wire [7:0] switches = 8'b0;
 134         wire [3:0] buttons = 4'b0;
 135 `else
 136         wire xtalb, clk, vgaclk;
 137         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 138         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 139         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 140 `endif
 141
 142         wire [15:0] addr [1:0];
 143         wire [7:0] data [1:0];
 144         wire wr [1:0], rd [1:0];
 145
 146         wire irq, tmrirq, lcdcirq, vblankirq;
 147         wire [7:0] jaddr;
 148         wire [1:0] state;
 149
 150         GBZ80Core core(
 151                 .clk(clk),
 152                 .bus0address(addr[0]),
 153                 .bus0data(data[0]),
 154                 .bus0wr(wr[0]),
 155                 .bus0rd(rd[0]),
 156                 .bus1address(addr[1]),
 157                 .bus1data(data[1]),
 158                 .bus1wr(wr[1]),
 159                 .bus1rd(rd[1]),
 160                 .irq(irq),
 161                 .jaddr(jaddr),
 162                 .state(state));
 163
 164         BootstrapROM brom(
 165                 .address(addr[1]),
 166                 .data(data[1]),
 167                 .clk(clk),
 168                 .wr(wr[1]),
 169                 .rd(rd[1]));
 170
 171         ROM rom(
 172                 .address(addr[0]),
 173                 .data(data[0]),
 174                 .clk(clk),
 175                 .wr(wr[0]),
 176                 .rd(rd[0]));
 177
 178         wire lcdhs, lcdvs, lcdclk;
 179         wire [2:0] lcdr, lcdg;
 180         wire [1:0] lcdb;
 181
 182         LCDC lcdc(
 183                 .clk(clk),
 184                 .addr(addr[0]),
 185                 .data(data[0]),
 186                 .wr(wr[0]),
 187                 .rd(rd[0]),
 188                 .lcdcirq(lcdcirq),
 189                 .vblankirq(vblankirq),
 190                 .lcdclk(lcdclk),
 191                 .lcdhs(lcdhs),
 192                 .lcdvs(lcdvs),
 193                 .lcdr(lcdr),
 194                 .lcdg(lcdg),
 195                 .lcdb(lcdb));
 196
 197         Framebuffer fb(
 198                 .lcdclk(lcdclk),
 199                 .lcdhs(lcdhs),
 200                 .lcdvs(lcdvs),
 201                 .lcdr(lcdr),
 202                 .lcdg(lcdg),
 203                 .lcdb(lcdb),
 204                 .vgaclk(vgaclk),
 205                 .vgahs(hs),
 206                 .vgavs(vs),
 207                 .vgar(r),
 208                 .vgag(g),
 209                 .vgab(b));
 210
 211         AddrMon amon(
 212                 .clk(clk),
 213                 .addr(addr[0]),
 214                 .digit(digits),
 215                 .out(seven),
 216                 .freeze(buttons[0]),
 217                 .periods(
 218                         (state == 2'b00) ? 4'b0010 :
 219                         (state == 2'b01) ? 4'b0001 :
 220                         (state == 2'b10) ? 4'b1000 :
 221                                            4'b0100) );
 222
 223         Switches sw(
 224                 .clk(clk),
 225                 .address(addr[0]),
 226                 .data(data[0]),
 227                 .wr(wr[0]),
 228                 .rd(rd[0]),
 229                 .ledout(leds),
 230                 .switches(switches)
 231                 );
 232
 233         UART nouart (   /* no u */
 234                 .clk(clk),
 235                 .addr(addr[0]),
 236                 .data(data[0]),
 237                 .wr(wr[0]),
 238                 .rd(rd[0]),
 239                 .serial(serio)
 240                 );
 241
 242         InternalRAM ram(
 243                 .clk(clk),
 244                 .address(addr[0]),
 245                 .data(data[0]),
 246                 .wr(wr[0]),
 247                 .rd(rd[0])
 248                 );
 249
 250         MiniRAM mram(
 251                 .clk(clk),
 252                 .address(addr[1]),
 253                 .data(data[1]),
 254                 .wr(wr[1]),
 255                 .rd(rd[1])
 256                 );
 257
 258         Timer tmr(
 259                 .clk(clk),
 260                 .addr(addr[0]),
 261                 .data(data[0]),
 262                 .wr(wr[0]),
 263                 .rd(rd[0]),
 264                 .irq(tmrirq)
 265                 );
 266
 267         Interrupt intr(
 268                 .clk(clk),
 269                 .addr(addr[0]),
 270                 .data(data[0]),
 271                 .wr(wr[0]),
 272                 .rd(rd[0]),
 273                 .vblank(vblankirq),
 274                 .lcdc(lcdcirq),
 275                 .tovf(tmrirq),
 276                 .serial(1'b0),
 277                 .buttons(1'b0),
 278                 .master(irq),
 279                 .jaddr(jaddr));
 280
 281         Soundcore sound(
 282                 .core_clk(clk),
 283                 .addr(addr[0]),
 284                 .data(data[0]),
 285                 .rd(rd[0]),
 286                 .wr(wr[0]),
 287                 .snd_data_l(soundl),
 288                 .snd_data_r(soundr));
 289 endmodule