firearm.git
10 years agoExecute: Fix carry flag on subtraction operations.
Joshua Wise [Fri, 23 Jan 2009 12:37:25 +0000 (07:37 -0500)]
Execute: Fix carry flag on subtraction operations.

10 years agoIssue: Fix case in which lr is read in the instruction immediately after a bl; now...
Joshua Wise [Fri, 23 Jan 2009 09:58:39 +0000 (04:58 -0500)]
Issue: Fix case in which lr is read in the instruction immediately after a bl; now flushes no longer clear inflight registers (which makes this a superset of the correct behavior), and now def_regs, well, defines regs.  This fixed the miniblarg -O1 bug.

10 years agotests/testbench: Commit new .hex file built with -O3 (2fast2furious).
Joshua Wise [Thu, 22 Jan 2009 07:59:51 +0000 (02:59 -0500)]
tests/testbench: Commit new .hex file built with -O3 (2fast2furious).

10 years agoExecute: Branches allow somebody else to take precedence by not branching if outstall...
Joshua Wise [Thu, 22 Jan 2009 07:59:16 +0000 (02:59 -0500)]
Execute: Branches allow somebody else to take precedence by not branching if outstall is asserted.  outstall must be low for at least one clock cycle, so the branch is guaranteed to eventually happen if it is in fact legitimate and not shot down.

10 years agoFetch: Allow new queued jumps to take precedence over old queued jumps (i.e., ldm...
Joshua Wise [Thu, 22 Jan 2009 07:58:24 +0000 (02:58 -0500)]
Fetch: Allow new queued jumps to take precedence over old queued jumps (i.e., ldm followed by bl; the bl happens first, but the ldm is what we really want in the end)

10 years agosystem, Writeback, Memory, Execute: Only update the CPSR when an update is specified...
Joshua Wise [Thu, 22 Jan 2009 07:09:09 +0000 (02:09 -0500)]
system, Writeback, Memory, Execute: Only update the CPSR when an update is specified (and expected by Issue).

10 years agoDCache/ICache: reg i -> integer i
Joshua Wise [Wed, 21 Jan 2009 20:31:18 +0000 (15:31 -0500)]
DCache/ICache: reg i -> integer i

10 years agoIssue: Fix use_regs for LDRSTR when not acting on an immediate value.
Joshua Wise [Mon, 19 Jan 2009 16:16:57 +0000 (11:16 -0500)]
Issue: Fix use_regs for LDRSTR when not acting on an immediate value.

10 years agoMemory: Fix the case where a LDM/LDR/LDRH/STM/STR/STRH would not get rejected if...
Joshua Wise [Mon, 19 Jan 2009 09:28:32 +0000 (04:28 -0500)]
Memory: Fix the case where a LDM/LDR/LDRH/STM/STR/STRH would not get rejected if stall was asserted because of a wait.

10 years agoMemory: Add one more state to lsr/lsrh/lsm to force the writeback to be committed...
Joshua Wise [Mon, 19 Jan 2009 09:05:47 +0000 (04:05 -0500)]
Memory: Add one more state to lsr/lsrh/lsm to force the writeback to be committed.  This is kind of a gross hack, but it can be fixed later with a 'busy' flag that gets set in the middle of a multi-cycle instruction that would get checked by the delayedflush logic.  Also, make sure that we do not progress past the first stage if a flush is requested while we're on the first stage, as would happen if we had an ldr right after a ldr pc, ...

10 years agoMemory: Fix bug in which multiplies would cause a HDATA access. Fix bug in which...
Joshua Wise [Sun, 18 Jan 2009 10:50:10 +0000 (05:50 -0500)]
Memory: Fix bug in which multiplies would cause a HDATA access.  Fix bug in which LDRSTR would always do a regfile write, trashing a register on a STR instruction. (!)

10 years agotests/testbench: Add miniblarg. Put ldm_bonehead in a place where it will not get...
Joshua Wise [Sun, 18 Jan 2009 09:19:52 +0000 (04:19 -0500)]
tests/testbench: Add miniblarg.  Put ldm_bonehead in a place where it will not get owned by -O3.

10 years agotests/Makefile: Add CFLAGS for LOL2FAST2FURIOUS.
Joshua Wise [Sun, 18 Jan 2009 09:19:11 +0000 (04:19 -0500)]
tests/Makefile: Add CFLAGS for LOL2FAST2FURIOUS.

10 years agoMemory: Change offset latch in LDM so that there is no flutter if DCache cannot get...
Joshua Wise [Sun, 18 Jan 2009 09:18:45 +0000 (04:18 -0500)]
Memory: Change offset latch in LDM so that there is no flutter if DCache cannot get the bus or tries to write to an address that has latency.

10 years agotests/testbench: Update output formatting for testbench.
Joshua Wise [Sat, 17 Jan 2009 11:15:01 +0000 (06:15 -0500)]
tests/testbench: Update output formatting for testbench.

10 years agoDCache/ICache: Invalidate while filling, so if the fill is aborted, then at least...
Joshua Wise [Sat, 17 Jan 2009 11:09:41 +0000 (06:09 -0500)]
DCache/ICache: Invalidate while filling, so if the fill is aborted, then at least we do not return bad data later.  8 hour debug session; 1 line fix.

10 years agotests/testbench: Allow compilation on x86.
Joshua Wise [Thu, 15 Jan 2009 08:35:37 +0000 (03:35 -0500)]
tests/testbench: Allow compilation on x86.

10 years agoDCache: Be more verbose about fills.
Joshua Wise [Thu, 15 Jan 2009 07:44:48 +0000 (02:44 -0500)]
DCache: Be more verbose about fills.

10 years agoBlockRAM: Write before read so that reads the next cycle return the right answer.
Joshua Wise [Thu, 15 Jan 2009 07:44:23 +0000 (02:44 -0500)]
BlockRAM: Write before read so that reads the next cycle return the right answer.

10 years agoExecute: fix rdiff
Joshua Wise [Thu, 15 Jan 2009 06:37:52 +0000 (01:37 -0500)]
Execute: fix rdiff

10 years agoMemory: Add delayed flush. Make outbubble correct by moving it to the end (sadface...
Joshua Wise [Wed, 14 Jan 2009 07:22:48 +0000 (02:22 -0500)]
Memory: Add delayed flush.  Make outbubble correct by moving it to the end (sadface).  Correct behavior in ldmstm if it has to rw_wait.  Make ldmstm more verbose.

10 years agoExecute: Fix outbubble on multiplier so that it remembers to flush, fixing ldm_bonehe...
Joshua Wise [Wed, 14 Jan 2009 07:20:50 +0000 (02:20 -0500)]
Execute: Fix outbubble on multiplier so that it remembers to flush, fixing ldm_bonehead test.

10 years agoExecute: Add delayed flush logic.
Joshua Wise [Wed, 14 Jan 2009 07:18:35 +0000 (02:18 -0500)]
Execute: Add delayed flush logic.

10 years agoICache and DCache: Do not accept fill data if the bus_ready is actually intended...
Joshua Wise [Wed, 14 Jan 2009 07:14:19 +0000 (02:14 -0500)]
ICache and DCache: Do not accept fill data if the bus_ready is actually intended for someone *else*.

10 years agoIssue: Add logic to defer a flush if need be (i.e., we're stalled at the time and...
Joshua Wise [Wed, 14 Jan 2009 07:13:25 +0000 (02:13 -0500)]
Issue: Add logic to defer a flush if need be (i.e., we're stalled at the time and hence not allowed to change any other state).

10 years agotests/costas: respin .hex
Joshua Wise [Wed, 14 Jan 2009 07:12:26 +0000 (02:12 -0500)]
tests/costas: respin .hex

10 years agotests: Add the new testbench.
Joshua Wise [Wed, 14 Jan 2009 07:10:56 +0000 (02:10 -0500)]
tests: Add the new testbench.

10 years agoanulib: move the stack ALL the way up
Joshua Wise [Wed, 14 Jan 2009 07:10:08 +0000 (02:10 -0500)]
anulib: move the stack ALL the way up

10 years agoFetch: Also queue up a jump if we are stalled.
Joshua Wise [Wed, 14 Jan 2009 05:57:29 +0000 (00:57 -0500)]
Fetch: Also queue up a jump if we are stalled.

10 years agoDCache: Change verbosity.
Joshua Wise [Tue, 13 Jan 2009 08:43:36 +0000 (03:43 -0500)]
DCache: Change verbosity.

10 years agosystem: Swap ICache and DCache in arbiter order.
Joshua Wise [Tue, 13 Jan 2009 08:40:57 +0000 (03:40 -0500)]
system: Swap ICache and DCache in arbiter order.

10 years agoanulib: Move the stack up.
Joshua Wise [Tue, 13 Jan 2009 08:40:33 +0000 (03:40 -0500)]
anulib: Move the stack up.

10 years agoCostas: Remove while(1) and allow proper returns.
Joshua Wise [Sun, 11 Jan 2009 05:27:56 +0000 (00:27 -0500)]
Costas: Remove while(1) and allow proper returns.

10 years agoMemory: Instrument LDMSTM. Do not write back if writeback not requested. Comment...
Joshua Wise [Sun, 11 Jan 2009 05:27:25 +0000 (00:27 -0500)]
Memory: Instrument LDMSTM.  Do not write back if writeback not requested.  Comment some magic bits.  Fix swapped cur_reg conditional.  Add pc save.

10 years agoDCache: Add instrumentation.
Joshua Wise [Sun, 11 Jan 2009 05:21:32 +0000 (00:21 -0500)]
DCache: Add instrumentation.

10 years agoMemory: Fix FSM for LDR/STR. Fix pre/post increment to be, uh, pre/post increment...
Joshua Wise [Sun, 11 Jan 2009 04:41:07 +0000 (23:41 -0500)]
Memory: Fix FSM for LDR/STR.  Fix pre/post increment to be, uh, pre/post increment, not post/pre increment.

10 years agoDecode: Fix conditional for immediate mode.
Joshua Wise [Sat, 10 Jan 2009 09:53:40 +0000 (04:53 -0500)]
Decode: Fix conditional for immediate mode.

10 years agosystem: Fix message printed by DECODE debug line to have a zero base for op numbers.
Joshua Wise [Sat, 10 Jan 2009 09:49:10 +0000 (04:49 -0500)]
system: Fix message printed by DECODE debug line to have a zero base for op numbers.

10 years agoEnable part 2 of the Costas test program.
Joshua Wise [Sat, 10 Jan 2009 09:35:53 +0000 (04:35 -0500)]
Enable part 2 of the Costas test program.

10 years agoAdd tests directory.
Joshua Wise [Sat, 10 Jan 2009 09:11:45 +0000 (04:11 -0500)]
Add tests directory.

10 years agoDCache, ICache: Reset fill circuitry if a request is aborted while filling.
Joshua Wise [Sat, 10 Jan 2009 09:07:51 +0000 (04:07 -0500)]
DCache, ICache: Reset fill circuitry if a request is aborted while filling.

10 years agoFetch: qjmp is for queueing up jumps while rd_waiting, not while stalled.
Joshua Wise [Sat, 10 Jan 2009 09:04:58 +0000 (04:04 -0500)]
Fetch: qjmp is for queueing up jumps while rd_waiting, not while stalled.

10 years agosystem: Print the correct values for jmp for Execute.
Joshua Wise [Sat, 10 Jan 2009 09:01:13 +0000 (04:01 -0500)]
system: Print the correct values for jmp for Execute.

10 years agoDCache: Fix silly bug involving failing to clear bus_wr.
Joshua Wise [Sat, 10 Jan 2009 08:48:06 +0000 (03:48 -0500)]
DCache: Fix silly bug involving failing to clear bus_wr.

10 years agoFetch: Rewrite to be cleaner.
Joshua Wise [Sat, 10 Jan 2009 08:26:03 +0000 (03:26 -0500)]
Fetch: Rewrite to be cleaner.

10 years agoTerminal: Add `ifdef verilator around the $c construct.
Joshua Wise [Sat, 10 Jan 2009 05:54:59 +0000 (00:54 -0500)]
Terminal: Add `ifdef verilator around the $c construct.

10 years agosystem: Fix bug that would cause stmia not to work.
Joshua Wise [Sat, 10 Jan 2009 05:53:52 +0000 (00:53 -0500)]
system: Fix bug that would cause stmia not to work.

10 years agoMemory: wire -> reg in some cases
Joshua Wise [Sat, 10 Jan 2009 05:51:00 +0000 (00:51 -0500)]
Memory: wire -> reg in some cases

10 years agoICache: Add instrumentation.
Joshua Wise [Sat, 10 Jan 2009 05:50:06 +0000 (00:50 -0500)]
ICache: Add instrumentation.

10 years agoExecute: Fix jumps while flush asserted. Set lr correctly in bl.
Joshua Wise [Sat, 10 Jan 2009 04:36:15 +0000 (23:36 -0500)]
Execute: Fix jumps while flush asserted.  Set lr correctly in bl.

10 years agoMerge branch 'master' of nyus.joshuawise.com:/git/firearm
Christopher Lu [Sat, 10 Jan 2009 03:18:37 +0000 (22:18 -0500)]
Merge branch 'master' of nyus.joshuawise.com:/git/firearm

10 years agounique values for the shits
Christopher Lu [Sat, 10 Jan 2009 03:18:33 +0000 (22:18 -0500)]
unique values for the shits

10 years agoram: Add a string printing test, WHICH WORKS!
Joshua Wise [Fri, 9 Jan 2009 09:25:56 +0000 (04:25 -0500)]
ram: Add a string printing test, WHICH WORKS!

10 years agoDecode: Fix stupid bug in which stalls did not stall the decoder.
Joshua Wise [Fri, 9 Jan 2009 09:25:36 +0000 (04:25 -0500)]
Decode: Fix stupid bug in which stalls did not stall the decoder.

10 years agoMerge nyus:/storage/git/firearm
Joshua Wise [Fri, 9 Jan 2009 09:02:54 +0000 (04:02 -0500)]
Merge nyus:/storage/git/firearm

Conflicts:

Memory.v

10 years agoAdd 'mov r1, #':' to ramfile.
Joshua Wise [Fri, 9 Jan 2009 09:02:05 +0000 (04:02 -0500)]
Add 'mov r1, #':' to ramfile.

10 years agoHit all with the integrate.
Joshua Wise [Fri, 9 Jan 2009 09:01:50 +0000 (04:01 -0500)]
Hit all with the integrate.

10 years agoWriteback: add
Joshua Wise [Fri, 9 Jan 2009 09:01:19 +0000 (04:01 -0500)]
Writeback: add

10 years agomemory: fix
Christopher Lu [Fri, 9 Jan 2009 08:52:31 +0000 (03:52 -0500)]
memory: fix

10 years agodecode: stuff for halfword
Christopher Lu [Fri, 9 Jan 2009 08:27:27 +0000 (03:27 -0500)]
decode: stuff for halfword

10 years agomemory wea
Christopher Lu [Fri, 9 Jan 2009 08:13:49 +0000 (03:13 -0500)]
memory wea

10 years agoblockram: more fix
Christopher Lu [Fri, 9 Jan 2009 06:27:12 +0000 (01:27 -0500)]
blockram: more fix

10 years agoMerge branch 'master' of nyus.joshuawise.com:/git/firearm
Christopher Lu [Fri, 9 Jan 2009 06:24:18 +0000 (01:24 -0500)]
Merge branch 'master' of nyus.joshuawise.com:/git/firearm

10 years agoblockram: fix hack, memory: add ldrh/strh
Christopher Lu [Fri, 9 Jan 2009 06:24:10 +0000 (01:24 -0500)]
blockram: fix hack, memory: add ldrh/strh

10 years agoram.hex: Add performance benchmark, P-SPEC 2009.
Joshua Wise [Fri, 9 Jan 2009 06:20:46 +0000 (01:20 -0500)]
ram.hex: Add performance benchmark, P-SPEC 2009.

10 years agoMemory: Add some debugging.
Joshua Wise [Fri, 9 Jan 2009 06:20:11 +0000 (01:20 -0500)]
Memory: Add some debugging.

10 years agoAdd terminal
Joshua Wise [Fri, 9 Jan 2009 06:19:12 +0000 (01:19 -0500)]
Add terminal

10 years agosystem: Wire up outcpsr and outspsr from Execute to Memory.
Joshua Wise [Wed, 7 Jan 2009 09:59:41 +0000 (04:59 -0500)]
system: Wire up outcpsr and outspsr from Execute to Memory.

10 years agoDecode: Set correct rpc for coprocessor register transfer.
Joshua Wise [Wed, 7 Jan 2009 09:59:24 +0000 (04:59 -0500)]
Decode: Set correct rpc for coprocessor register transfer.

10 years agoAdd special CPSR behavior for ARM MCR.
Joshua Wise [Wed, 7 Jan 2009 09:58:34 +0000 (04:58 -0500)]
Add special CPSR behavior for ARM MCR.

10 years agoAdd LDR test instruction.
Joshua Wise [Wed, 7 Jan 2009 09:58:14 +0000 (04:58 -0500)]
Add LDR test instruction.

10 years agomemory: bubble
Christopher Lu [Wed, 7 Jan 2009 09:54:31 +0000 (04:54 -0500)]
memory: bubble

10 years agomemory: merged
Christopher Lu [Wed, 7 Jan 2009 09:45:21 +0000 (04:45 -0500)]
memory: merged

10 years agomemory.v: convert to state machines
Christopher Lu [Wed, 7 Jan 2009 09:44:03 +0000 (04:44 -0500)]
memory.v: convert to state machines

10 years agoMemory: Add CDP and MRC/MCR.
Joshua Wise [Wed, 7 Jan 2009 09:25:50 +0000 (04:25 -0500)]
Memory: Add CDP and MRC/MCR.

10 years agoMerge nyus:/storage/git/firearm
Joshua Wise [Wed, 7 Jan 2009 08:08:46 +0000 (03:08 -0500)]
Merge nyus:/storage/git/firearm

Conflicts:

Memory.v

10 years agoMemory: Add coprocessor interface stub.
Joshua Wise [Wed, 7 Jan 2009 08:08:22 +0000 (03:08 -0500)]
Memory: Add coprocessor interface stub.

10 years agomemory: ldm/stm bullSHIT
Christopher Lu [Wed, 7 Jan 2009 07:38:53 +0000 (02:38 -0500)]
memory: ldm/stm bullSHIT

10 years agomemory: ldm/stm ready for testing, hopefully
Christopher Lu [Wed, 7 Jan 2009 07:10:13 +0000 (02:10 -0500)]
memory: ldm/stm ready for testing, hopefully

10 years agomerge memory
Christopher Lu [Tue, 6 Jan 2009 08:20:31 +0000 (03:20 -0500)]
merge memory

10 years agomemory: more ldm/stm
Christopher Lu [Tue, 6 Jan 2009 08:18:00 +0000 (03:18 -0500)]
memory: more ldm/stm

10 years agosystem: Remember to wire the DCache to the memory!
Joshua Wise [Tue, 6 Jan 2009 08:17:27 +0000 (03:17 -0500)]
system: Remember to wire the DCache to the memory!

10 years agoWire in Memory. Fix small bug in Memory involving registers never ever getting outpu...
Joshua Wise [Tue, 6 Jan 2009 08:15:58 +0000 (03:15 -0500)]
Wire in Memory.  Fix small bug in Memory involving registers never ever getting output (type A...).

10 years agoMerge branch 'master' of nyus.joshuawise.com:/git/firearm
Christopher Lu [Tue, 6 Jan 2009 07:52:28 +0000 (02:52 -0500)]
Merge branch 'master' of nyus.joshuawise.com:/git/firearm

10 years agomemory: more ldm/stm
Christopher Lu [Tue, 6 Jan 2009 07:52:24 +0000 (02:52 -0500)]
memory: more ldm/stm

10 years agost_data -> op2
Joshua Wise [Tue, 6 Jan 2009 07:50:55 +0000 (02:50 -0500)]
st_data -> op2

10 years agoMerge Memory.
Joshua Wise [Tue, 6 Jan 2009 07:31:00 +0000 (02:31 -0500)]
Merge Memory.

10 years agomemory: add some stuff in ldm/stm
Christopher Lu [Tue, 6 Jan 2009 07:27:04 +0000 (02:27 -0500)]
memory: add some stuff in ldm/stm

10 years agoMemory.v: Cleanup pass 1 before integration.
Joshua Wise [Tue, 6 Jan 2009 07:24:32 +0000 (02:24 -0500)]
Memory.v: Cleanup pass 1 before integration.

10 years agoMerge nyus:/storage/git/firearm
Joshua Wise [Tue, 6 Jan 2009 06:39:55 +0000 (01:39 -0500)]
Merge nyus:/storage/git/firearm

10 years agomemory: fix up slightly
Christopher Lu [Tue, 6 Jan 2009 06:39:32 +0000 (01:39 -0500)]
memory: fix up slightly

10 years agoMerge nyus:/storage/git/firearm
Joshua Wise [Tue, 6 Jan 2009 06:34:57 +0000 (01:34 -0500)]
Merge nyus:/storage/git/firearm

10 years agomemory: fixed up a bit
Christopher Lu [Tue, 6 Jan 2009 06:34:42 +0000 (01:34 -0500)]
memory: fixed up a bit

10 years agoMerge nyus:/storage/git/firearm
Joshua Wise [Tue, 6 Jan 2009 06:11:11 +0000 (01:11 -0500)]
Merge nyus:/storage/git/firearm

10 years agomemory: preliminary, regfile: more read port, decode: more correct
Christopher Lu [Tue, 6 Jan 2009 06:06:00 +0000 (01:06 -0500)]
memory: preliminary, regfile: more read port, decode: more correct

10 years agoSystem.v: Wire up DCache
Joshua Wise [Tue, 6 Jan 2009 05:53:29 +0000 (00:53 -0500)]
System.v: Wire up DCache

10 years agosystem.v: Silly typo fix -- why didn't Verilator warn me about that?????
Joshua Wise [Tue, 6 Jan 2009 04:57:24 +0000 (23:57 -0500)]
system.v: Silly typo fix -- why didn't Verilator warn me about that?????

10 years agoExecute.v: Add outpc and outinsn. System.v: Add and make wires consistent.
Joshua Wise [Tue, 6 Jan 2009 03:21:53 +0000 (22:21 -0500)]
Execute.v: Add outpc and outinsn. System.v: Add and make wires consistent.

10 years agoAdd the DCache.
Joshua Wise [Tue, 6 Jan 2009 03:20:53 +0000 (22:20 -0500)]
Add the DCache.

10 years agoOk, it work.
Joshua Wise [Mon, 5 Jan 2009 10:26:19 +0000 (05:26 -0500)]
Ok, it work.

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