Writeback: add
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 Jan 2009 09:01:19 +0000 (04:01 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 Jan 2009 09:01:19 +0000 (04:01 -0500)
Writeback.v [new file with mode: 0644]

diff --git a/Writeback.v b/Writeback.v
new file mode 100644 (file)
index 0000000..b0e69cf
--- /dev/null
@@ -0,0 +1,63 @@
+module Writeback(
+       input clk,
+       
+       input inbubble,
+       
+       input write_reg,
+       input [3:0] write_num,
+       input [31:0] write_data,
+       
+       input [31:0] cpsr,
+       input [31:0] spsr,
+       
+       output reg regfile_write,
+       output reg [3:0] regfile_write_reg,
+       output reg [31:0] regfile_write_data,
+       
+       output reg [31:0] outcpsr,
+       output reg [31:0] outspsr,
+       
+       output reg jmp,
+       output reg [31:0] jmppc);
+       
+       reg [31:0] last_outcpsr = 0, last_outspsr = 0;
+       
+       always @(*)
+               if (inbubble)
+                       outcpsr = last_outcpsr;
+               else
+                       outcpsr = cpsr;
+       
+       always @(*)
+               if (inbubble)
+                       outspsr = last_outspsr;
+               else
+                       outspsr = spsr;
+       
+       always @(*)
+       begin
+               regfile_write = 0;
+               regfile_write_reg = 4'hx;
+               regfile_write_data = 32'hxxxxxxxx;
+               jmp = 0;
+               jmppc = 32'h00000000;
+               if (!inbubble)
+               begin
+                       if (write_reg && (write_num != 15))
+                       begin
+                               regfile_write = 1;
+                               regfile_write_reg = write_num;
+                               regfile_write_data = write_data;
+                       end else if (write_reg && (write_num == 15)) begin
+                               jmp = 1;
+                               jmppc = write_data;
+                       end
+               end
+       end
+       
+       always @(posedge clk)
+       begin
+               last_outspsr <= outspsr;
+               last_outcpsr <= outcpsr;
+       end
+endmodule
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