BlockRAM: Write before read so that reads the next cycle return the right answer.

diff --git a/BlockRAM.v b/BlockRAM.v
index a86ec7592ad0f5a315977d54319e2b3ad56cd6df..e0eceeb8009caa4c458c95301ca5666d6fb8e09a 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -31,7 +31,7 @@ module BlockRAM(
        always @(posedge clk)
        begin
                if (bus_wr && decode)
-                       data[ramaddr[13:2]] <= bus_wdata;
+                       data[ramaddr[13:2]] = bus_wdata;
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */