Memory: Add one more state to lsr/lsrh/lsm to force the writeback to be committed...

Memory: Add one more state to lsr/lsrh/lsm to force the writeback to be committed.  This is kind of a gross hack, but it can be fixed later with a 'busy' flag that gets set in the middle of a multi-cycle instruction that would get checked by the delayedflush logic.  Also, make sure that we do not progress past the first stage if a flush is requested while we're on the first stage, as would happen if we had an ldr right after a ldr pc, ...