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(parent: c4e2ac3) | patch
ICache and DCache: Do not accept fill data if the bus_ready is actually intended...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Wed, 14 Jan 2009 07:14:19 +0000 (02:14 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Wed, 14 Jan 2009 07:14:19 +0000 (02:14 -0500)
commit52fd78ff62b919c5dd5e59af2550e4ff733816a1
tree0abe7c8be4857ba71e40bbc501e80891cd486b94tree | snapshot
parentc4e2ac3b3f80b9d92660c87009714362cdb7f875commit | diff
ICache and DCache: Do not accept fill data if the bus_ready is actually intended for someone *else*.
DCache.v diff | blob | blame | history
ICache.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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