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Commit | Line | Data |
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ee406839 JW |
1 | `define BUS_ICACHE 0 |
2 | ||
f61f8d6f | 3 | module System(input clk); |
ee406839 JW |
4 | wire [7:0] bus_req; |
5 | wire [7:0] bus_ack; | |
6 | wire [31:0] bus_addr; | |
a0bb35e7 JW |
7 | wire [31:0] bus_rdata; |
8 | wire [31:0] bus_wdata; | |
ee406839 JW |
9 | wire bus_rd, bus_wr; |
10 | wire bus_ready; | |
45fa96c0 JW |
11 | |
12 | wire bus_req_icache; | |
13 | assign bus_req = {7'b0, bus_req_icache}; | |
ee406839 | 14 | wire bus_ack_icache = bus_ack[`BUS_ICACHE]; |
45fa96c0 | 15 | |
ee406839 JW |
16 | wire [31:0] bus_addr_icache; |
17 | wire [31:0] bus_wdata_icache; | |
18 | wire bus_rd_icache; | |
19 | wire bus_wr_icache; | |
20 | ||
a0bb35e7 JW |
21 | wire [31:0] bus_rdata_blockram; |
22 | wire bus_ready_blockram; | |
23 | ||
ee406839 | 24 | assign bus_addr = bus_addr_icache; |
a0bb35e7 JW |
25 | assign bus_rdata = bus_rdata_blockram; |
26 | assign bus_wdata = bus_wdata_icache; | |
ee406839 JW |
27 | assign bus_rd = bus_rd_icache; |
28 | assign bus_wr = bus_wr_icache; | |
a0bb35e7 | 29 | assign bus_ready = bus_ready_blockram; |
149bcd1a | 30 | |
5d9760a4 JW |
31 | wire [31:0] icache_rd_addr; |
32 | wire icache_rd_req; | |
33 | wire icache_rd_wait; | |
34 | wire [31:0] icache_rd_data; | |
09e28f01 JW |
35 | |
36 | wire stall_cause_issue; | |
bc572c5f | 37 | wire stall_cause_execute; |
09e28f01 | 38 | |
cb0428b6 | 39 | wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr; |
42c1e610 | 40 | wire decode_out_carry; |
5ca27949 | 41 | wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2; |
cb0428b6 | 42 | wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr; |
bc572c5f JW |
43 | wire execute_out_stall, execute_out_bubble; |
44 | wire execute_out_write_reg; | |
45 | wire [3:0] execute_out_write_num; | |
46 | wire [31:0] execute_out_write_data; | |
149bcd1a CL |
47 | wire [31:0] jmppc; |
48 | wire jmp; | |
5ca27949 | 49 | |
09e28f01 JW |
50 | wire bubble_out_fetch; |
51 | wire bubble_out_issue; | |
52 | wire [31:0] insn_out_fetch; | |
53 | wire [31:0] insn_out_issue; | |
54 | wire [31:0] pc_out_fetch; | |
55 | wire [31:0] pc_out_issue; | |
149bcd1a | 56 | |
c2b9d4b7 CL |
57 | wire execute_outflush = jmp; |
58 | wire issue_flush = execute_outflush; | |
59 | wire execute_flush = 1'b0; | |
60 | ||
ee406839 | 61 | BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack)); |
a0bb35e7 JW |
62 | |
63 | ICache icache( | |
64 | .clk(clk), | |
5d9760a4 JW |
65 | /* XXX reset? */ |
66 | .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), | |
67 | .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), | |
ee406839 | 68 | .bus_req(bus_req_icache), .bus_ack(bus_ack_icache), |
a0bb35e7 | 69 | .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata), |
ee406839 JW |
70 | .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache), |
71 | .bus_wr(bus_wr_icache), .bus_ready(bus_ready)); | |
45fa96c0 | 72 | |
a0bb35e7 JW |
73 | BlockRAM blockram( |
74 | .clk(clk), | |
75 | .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram), | |
76 | .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr), | |
77 | .bus_ready(bus_ready_blockram)); | |
78 | ||
5d9760a4 JW |
79 | Fetch fetch( |
80 | .clk(clk), | |
f61f8d6f | 81 | .Nrst(1'b1 /* XXX */), |
5d9760a4 JW |
82 | .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), |
83 | .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), | |
149bcd1a | 84 | .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc), |
09e28f01 JW |
85 | .bubble(bubble_out_fetch), .insn(insn_out_fetch), |
86 | .pc(pc_out_fetch)); | |
87 | ||
88 | Issue issue( | |
89 | .clk(clk), | |
f61f8d6f | 90 | .Nrst(1'b1 /* XXX */), |
c2b9d4b7 | 91 | .stall(stall_cause_execute), .flush(issue_flush), |
09e28f01 | 92 | .inbubble(bubble_out_fetch), .insn(insn_out_fetch), |
f61f8d6f | 93 | .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */), |
09e28f01 JW |
94 | .outstall(stall_cause_issue), .outbubble(bubble_out_issue), |
95 | .outpc(pc_out_issue), .outinsn(insn_out_issue)); | |
90ff449a | 96 | |
5ca27949 JW |
97 | RegFile regfile( |
98 | .clk(clk), | |
99 | .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), | |
100 | .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), | |
cb0428b6 | 101 | .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */)); |
5ca27949 JW |
102 | |
103 | Decode decode( | |
104 | .clk(clk), | |
cb0428b6 | 105 | .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr), |
5ca27949 | 106 | .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2), |
cb0428b6 | 107 | .carry(decode_out_carry), .outspsr(decode_out_spsr), |
5ca27949 JW |
108 | .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), |
109 | .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2)); | |
110 | ||
bc572c5f | 111 | Execute execute( |
f61f8d6f | 112 | .clk(clk), .Nrst(1'b0), |
c2b9d4b7 | 113 | .stall(1'b0 /* XXX */), .flush(execute_flush), |
bc572c5f | 114 | .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue), |
cb0428b6 | 115 | .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1), |
bc572c5f JW |
116 | .op2(decode_out_op2), .carry(decode_out_carry), |
117 | .outstall(stall_cause_execute), .outbubble(execute_out_bubble), | |
118 | .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), | |
149bcd1a CL |
119 | .write_data(execute_out_write_data), |
120 | .jmppc(jmppc), | |
121 | .jmp(jmp)); | |
122 | ||
ff39dfc7 | 123 | reg [31:0] clockno = 0; |
90ff449a JW |
124 | always @(posedge clk) |
125 | begin | |
ff39dfc7 JW |
126 | clockno <= clockno + 1; |
127 | $display("------------------------------------------------------------------------------"); | |
5ca27949 JW |
128 | $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch); |
129 | $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue); | |
42c1e610 | 130 | $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry); |
acae28be | 131 | $display("%3d: EXEC: Stall: %d, Bubble: %d, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc); |
90ff449a | 132 | end |
ee406839 | 133 | endmodule |