Joshua Wise's Git repositories - firearm.git/blame_incremental

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Commit	Line	Data
	1	`define BUS_ICACHE 0
	2
	3	module System(input clk);
	4	wire [7:0] bus_req;
	5	wire [7:0] bus_ack;
	6	wire [31:0] bus_addr;
	7	wire [31:0] bus_rdata;
	8	wire [31:0] bus_wdata;
	9	wire bus_rd, bus_wr;
	10	wire bus_ready;
	11
	12	wire bus_req_icache;
	13	assign bus_req = {7'b0, bus_req_icache};
	14	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	15
	16	wire [31:0] bus_addr_icache;
	17	wire [31:0] bus_wdata_icache;
	18	wire bus_rd_icache;
	19	wire bus_wr_icache;
	20
	21	wire [31:0] bus_rdata_blockram;
	22	wire bus_ready_blockram;
	23
	24	assign bus_addr = bus_addr_icache;
	25	assign bus_rdata = bus_rdata_blockram;
	26	assign bus_wdata = bus_wdata_icache;
	27	assign bus_rd = bus_rd_icache;
	28	assign bus_wr = bus_wr_icache;
	29	assign bus_ready = bus_ready_blockram;
	30
	31	wire [31:0] icache_rd_addr;
	32	wire icache_rd_req;
	33	wire icache_rd_wait;
	34	wire [31:0] icache_rd_data;
	35
	36	wire stall_cause_issue;
	37	wire stall_cause_execute;
	38
	39	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
	40	wire decode_out_carry;
	41	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
	42	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
	43	wire execute_out_stall, execute_out_bubble;
	44	wire execute_out_write_reg;
	45	wire [3:0] execute_out_write_num;
	46	wire [31:0] execute_out_write_data;
	47	wire [31:0] jmppc;
	48	wire jmp;
	49
	50	wire bubble_out_fetch;
	51	wire bubble_out_issue;
	52	wire [31:0] insn_out_fetch;
	53	wire [31:0] insn_out_issue;
	54	wire [31:0] pc_out_fetch;
	55	wire [31:0] pc_out_issue;
	56
	57	wire execute_outflush = jmp;
	58	wire issue_flush = execute_outflush;
	59	wire execute_flush = 1'b0;
	60
	61	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
	62
	63	ICache icache(
	64	.clk(clk),
	65	/* XXX reset? */
	66	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
	67	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
	68	.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
	69	.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
	70	.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
	71	.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
	72
	73	BlockRAM blockram(
	74	.clk(clk),
	75	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	76	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	77	.bus_ready(bus_ready_blockram));
	78
	79	Fetch fetch(
	80	.clk(clk),
	81	.Nrst(1'b1 /* XXX */),
	82	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
	83	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
	84	.stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
	85	.bubble(bubble_out_fetch), .insn(insn_out_fetch),
	86	.pc(pc_out_fetch));
	87
	88	Issue issue(
	89	.clk(clk),
	90	.Nrst(1'b1 /* XXX */),
	91	.stall(stall_cause_execute), .flush(issue_flush),
	92	.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
	93	.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
	94	.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
	95	.outpc(pc_out_issue), .outinsn(insn_out_issue));
	96
	97	RegFile regfile(
	98	.clk(clk),
	99	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
	100	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
	101	.spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
	102
	103	Decode decode(
	104	.clk(clk),
	105	.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
	106	.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
	107	.carry(decode_out_carry), .outspsr(decode_out_spsr),
	108	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
	109	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	110
	111	Execute execute(
	112	.clk(clk), .Nrst(1'b0),
	113	.stall(1'b0 /* XXX */), .flush(execute_flush),
	114	.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
	115	.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
	116	.op2(decode_out_op2), .carry(decode_out_carry),
	117	.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
	118	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
	119	.write_data(execute_out_write_data),
	120	.jmppc(jmppc),
	121	.jmp(jmp));
	122
	123	reg [31:0] clockno = 0;
	124	always @(posedge clk)
	125	begin
	126	clockno <= clockno + 1;
	127	$display("------------------------------------------------------------------------------");
	128	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
	129	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
	130	$display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
	131	$display("%3d: EXEC: Stall: %d, Bubble: %d, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
	132	end
	133	endmodule