Holy crap, dropped lut count to 7640, and slice count to 4253
[mandelfpga.git] / Main.v
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cf1ae842 1/*
05c0805b
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2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
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12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
fb8d158b 67 output reg ovf);
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68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
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72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x[12:1]) : 0) +
74 (y[10] ? (x[12:2]) : 0)) +
75 (((y[9] ? (x[12:3]) : 0) +
76 (y[8] ? (x[12:4]) : 0)) +
77 ((y[7] ? (x[12:5]) : 0) +
78 (y[6] ? (x[12:6]) : 0))))+
79 (((y[5] ? (x[12:7]) : 0) +
80 (y[4] ? (x[12:8]) : 0) +
81 (y[3] ? (x[12:9]) : 0)) +
82 ((y[2] ? (x[12:10]): 0) +
83 (y[1] ? (x[12:11]): 0) +
84 (y[0] ? (x[12]): 0)));
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85 sign <= xsign ^ ysign;
86 end
87
88endmodule
89
90module Multiplier(
91 input clk,
92e851e1 92 input [12:0] x, y,
05c0805b 93 input xsign, ysign,
92e851e1 94 output wire [12:0] out,
05c0805b 95 output wire sign,
fb8d158b 96 output wire overflow);
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97
98 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
99
100endmodule
101
fb8d158b 102// Yuq.
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103module MandelUnit(
104 input clk,
105 input [12:0] x, y,
106 input xsign, ysign,
92e851e1 107 input [14:0] r, i,
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108 input rsign, isign,
109 input [7:0] ibail, icuriter,
110 output reg [12:0] xout, yout,
111 output reg xsout, ysout,
92e851e1 112 output reg [14:0] rout, iout,
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113 output reg rsout, isout,
114 output reg [7:0] obail, ocuriter);
115
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116 wire [13:0] r2, i2;
117 wire [14:0] ri, diff;
9032b2b5 118 wire [15:0] twocdiff;
05c0805b 119 wire r2sign, i2sign, risign, dsign;
02d0a24b 120 wire [14:0] bigsum;
6cdf39e2 121 wire bigsum_ovf;
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122
123 reg [12:0] xd, yd;
2afeab21 124 reg ineedbaild;
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125 reg xsd, ysd;
126 reg [7:0] ibaild, curiterd;
127
128 assign ri[0] = 0;
129
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130 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
131 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
132 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
05c0805b 133
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134 assign bigsum = r2[13:0] + i2[13:0];
135 wire shnasto = bigsum[14];
136 wire shnasto2 = // o shi
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137 ((r[13] & i[13]) |
138 ((r[13] ^ i[13]) &
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139 ((r[12] & i[12]) |
140 ((r[12] ^ i[12]) &
141 ((r[11] & i[11]) |
142 ((r[11] ^ i[11]) &
143 ((r[10] & i[10]) |
144 ((r[10] ^ i[10]) &
145 ((r[ 9] & i[ 9]) |
146 ((r[ 9] ^ i[ 9]) &
147 ((r[ 8] & i[ 8]) |
148 ((r[ 8] ^ i[ 8]) &
149 ((r[ 7] & i[ 7]) |
150 ((r[ 7] ^ i[ 7]) &
151 ((r[ 6] & i[ 6]) |
152 ((r[ 6] ^ i[ 6]) &
153 ((r[ 5] & i[ 5]) |
154 ((r[ 5] ^ i[ 5]) &
155 ((r[ 4] & i[ 4]) |
156 ((r[ 4] ^ i[ 4]) &
157 ((r[ 3] & i[ 3]) |
158 ((r[ 3] ^ i[ 3]) &
159 ((r[ 2] & i[ 2]) |
160 ((r[ 2] ^ i[ 2]) &
161 ((r[ 1] & i[ 1]) |
162 ((r[ 1] ^ i[ 1]) &
163 (r[ 0] & i[ 0])
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164 ))))))))))))))))))))))))));
165 assign bigsum_ovf = shnasto;
2afeab21 166
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167 assign twocdiff = r2 - i2;
168 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
169 assign dsign = twocdiff[15];
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170
171 wire [15:0] twocrout = xd - diff;
172 wire [15:0] twociout = yd - ri;
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173
174 always @ (posedge clk)
175 begin
176 xd <= x;
177 yd <= y;
178 xsd <= xsign;
179 ysd <= ysign;
180 xout <= xd;
181 yout <= yd;
182 xsout <= xsd;
183 ysout <= ysd;
184 ibaild <= ibail;
185 curiterd <= icuriter;
2afeab21 186 ineedbaild <= r[13] | r[14] | i[13] | i[14];
05c0805b 187
2afeab21 188 // r^2 - i^2 + x
05c0805b 189 if (xsd ^ dsign) begin
2afeab21
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190 if (twocrout[15]) begin // diff > xd
191 rout <= -twocrout;
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192 rsout <= dsign;
193 end else begin
2afeab21 194 rout <= twocrout;
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195 rsout <= xsd;
196 end
197 end else begin
198 rout <= diff + xd;
2afeab21 199 rsout <= xsd; // xsd == dsign
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200 end
201
2afeab21 202 // 2 * r * i + y
05c0805b 203 if (ysd ^ risign) begin
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204 if (twociout[15]) begin // ri > yd
205 iout <= -twociout;
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206 isout <= risign;
207 end else begin
2afeab21 208 iout <= twociout;
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209 isout <= ysd;
210 end
211 end else begin
212 iout <= ri + yd;
213 isout <= ysd;
214 end
215
216 // If we haven't bailed out, and we meet any of the bailout conditions,
217 // bail out now. Otherwise, leave the bailout at whatever it was before.
2afeab21 218 if ((ibaild == 255) && (bigsum_ovf | ineedbaild))
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219 obail <= curiterd;
220 else
221 obail <= ibaild;
222 ocuriter <= curiterd + 8'b1;
223 end
224
225endmodule
226
227module Mandelbrot(
228 input mclk,
229 input pixclk,
230 input [11:0] x, y,
92e851e1 231 input [13:0] xofs, yofs,
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232 input [7:0] colorofs,
233 input [2:0] scale,
234 output reg [2:0] red, green, output reg [1:0] blue);
281eac32 235
534b3903 236`define MAXOUTN 11
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237
238 wire [12:0] rx, ry;
239 wire [13:0] nx, ny;
240 wire rxsign, rysign;
241
242 assign nx = x + xofs;
243 assign ny = y + yofs;
244 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
245 assign rxsign = nx[13];
246 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
247 assign rysign = ny[13];
05c0805b 248
281eac32
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249 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
250 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
251 wire [7:0] mb[`MAXOUTN:0];
252 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
253 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
254 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 255
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256 reg [14:0] initx, inity, initr, initi;
257 reg [7:0] initci, initb;
258 reg initxs, initys, initrs, initis;
05c0805b 259
534b3903
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260 // Values after the number of iterations denoted by the subscript.
261 reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
262 reg [7:0] stageci [2:1], stageb [2:1];
263 reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b 264
534b3903 265 reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b 266
79af494a
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267 // States are advanced one from what they should be, so that they'll
268 // get there on the _next_ mclk.
269 always @(posedge mclk)
270 begin
271 initx <= (state[2]) ? rx :
272 (state[0]) ? stagex[1] :
273 (state[1]) ? stagex[2] : 0;
274 inity <= (state[2]) ? ry :
275 (state[0]) ? stagey[1] :
276 (state[1]) ? stagey[2] : 0;
277 initr <= (state[2]) ? rx :
278 (state[0]) ? stager[1] :
279 (state[1]) ? stager[2] : 0;
280 initi <= (state[2]) ? ry :
281 (state[0]) ? stagei[1] :
282 (state[1]) ? stagei[2] : 0;
283 initxs <= (state[2]) ? rxsign :
284 (state[0]) ? stagexs[1] :
285 (state[1]) ? stagexs[2] : 0;
286 initys <= (state[2]) ? rysign :
287 (state[0]) ? stageys[1] :
288 (state[1]) ? stageys[2] : 0;
289 initrs <= (state[2]) ? rxsign :
290 (state[0]) ? stagers[1] :
291 (state[1]) ? stagers[2] : 0;
292 initis <= (state[2]) ? rysign :
293 (state[0]) ? stageis[1] :
294 (state[1]) ? stageis[2] : 0;
295 initb <= (state[2]) ? 8'b11111111 :
296 (state[0]) ? stageb[1] :
297 (state[1]) ? stageb[2] : 0;
298 initci <= (state[2]) ? 8'b00000000 :
299 (state[0]) ? stageci[1] :
300 (state[1]) ? stageci[2] : 0;
301 end
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302
303 reg [7:0] out;
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304
305 // We detect when the state should be poked by a high negedge followed
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306 // by a high posedge -- if that happens, then we're guaranteed that the
307 // state following the current state will be 3'b100.
251788d8 308 reg lastneg;
265061f2 309 always @(negedge mclk)
251788d8 310 lastneg <= pixclk;
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311
312 always @(posedge mclk)
313 begin
251788d8
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314 if (lastneg && pixclk) // If a pixclk has happened, the state should be reset.
315 state <= 3'b100;
316 else // Otherwise, just poke it forward.
a3a4354b
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317 case(state)
318 3'b001: state <= 3'b010;
319 3'b010: state <= 3'b100;
320 3'b100: state <= 3'b001;
321 endcase
251788d8 322
534b3903
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323 // Data output handling
324 if (state[0]) begin
05c0805b 325 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b 326 end
3068fa61 327 if (state[1]) begin
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328 out <= ~mb[`MAXOUTN] + colorofs;
329 end
330
3068fa61 331 if (state[0]) begin // PnR0 in, PnR2 out
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332 stagex[2] <= xprop[`MAXOUTN];
333 stagey[2] <= yprop[`MAXOUTN];
334 stager[2] <= mr[`MAXOUTN];
335 stagei[2] <= mi[`MAXOUTN];
336 stagexs[2] <= xsprop[`MAXOUTN];
337 stageys[2] <= ysprop[`MAXOUTN];
338 stagers[2] <= mrs[`MAXOUTN];
339 stageis[2] <= mis[`MAXOUTN];
340 stageb[2] <= mb[`MAXOUTN];
341 stageci[2] <= curiter[`MAXOUTN];
342 end
343
3068fa61 344 if (state[2]) begin // PnR2 in, PnR1 out
534b3903
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345 stagex[1] <= xprop[`MAXOUTN];
346 stagey[1] <= yprop[`MAXOUTN];
347 stager[1] <= mr[`MAXOUTN];
348 stagei[1] <= mi[`MAXOUTN];
349 stagexs[1] <= xsprop[`MAXOUTN];
350 stageys[1] <= ysprop[`MAXOUTN];
351 stagers[1] <= mrs[`MAXOUTN];
352 stageis[1] <= mis[`MAXOUTN];
353 stageb[1] <= mb[`MAXOUTN];
354 stageci[1] <= curiter[`MAXOUTN];
355 end
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356 end
357
358 MandelUnit mu0(
359 mclk,
360 initx, inity, initxs, initys,
361 initr, initi, initrs, initis,
362 initb, initci,
363 xprop[0], yprop[0], xsprop[0], ysprop[0],
364 mr[0], mi[0], mrs[0], mis[0],
365 mb[0], curiter[0]);
e03ccef9
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366
367`define MAKE_UNIT(name, num) \
368 MandelUnit name(mclk, \
369 xprop[(num)], yprop[(num)], xsprop[(num)], ysprop[(num)], mr[(num)], mi[(num)], mrs[(num)], mis[(num)], mb[(num)], curiter[(num)], \
370 xprop[(num)+1], yprop[(num)+1], xsprop[(num)+1], ysprop[(num)+1], mr[(num)+1], mi[(num)+1], mrs[(num)+1], mis[(num)+1], mb[(num)+1], curiter[(num)+1])
05c0805b 371
e03ccef9
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372 `MAKE_UNIT(mu1, 0);
373 `MAKE_UNIT(mu2, 1);
374 `MAKE_UNIT(mu3, 2);
375 `MAKE_UNIT(mu4, 3);
376 `MAKE_UNIT(mu5, 4);
377 `MAKE_UNIT(mu6, 5);
378 `MAKE_UNIT(mu7, 6);
379 `MAKE_UNIT(mu8, 7);
380 `MAKE_UNIT(mu9, 8);
381 `MAKE_UNIT(mua, 9);
382 `MAKE_UNIT(mub, 10);
05c0805b
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383endmodule
384
385module Logo(
386 input pixclk,
387 input [11:0] x, y,
388 output wire enb,
389 output wire [2:0] red, green, output wire [1:0] blue);
390
391 reg [1:0] logo[8191:0];
392 initial $readmemb("logo.readmemb", logo);
393
394 assign enb = (x < 96) && (y < 64);
395 wire [12:0] addr = {y[5:0], x[6:0]};
396 wire [1:0] data = logo[addr];
397 assign {red, green, blue} =
398 (data == 2'b00) ? 8'b00000000 :
399 ((data == 2'b01) ? 8'b00011100 :
400 ((data == 2'b10) ? 8'b11100000 :
401 8'b11111111));
402endmodule
403
404module MandelTop(
405 input gclk, output wire dcmok,
406 output wire vs, hs,
407 output wire [2:0] red, green, output [1:0] blue,
408 input left, right, up, down, rst, cycle, logooff,
409 input [2:0] scale);
410
11cc2d9b 411 wire pixclk, mclk, clk;
534b3903 412 wire dcm1ok, dcm2ok;
c3ed4329 413 assign dcmok = dcm1ok && dcm2ok;
265061f2 414
e03ccef9 415 IBUFG iclkbuf(.O(clk), .I(gclk));
534b3903 416
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JW
417 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
418 .CLKIN_IN(clk),
419 .CLKFX_OUT(pixclk),
420 .LOCKED_OUT(dcm1ok)
421 );
534b3903 422
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JW
423 mandelDCM dcm2(
424 .CLKIN_IN(clk),
425 .CLKFX_OUT(mclk),
426 .LOCKED_OUT(dcm2ok)
427 );
534b3903 428
05c0805b 429 wire border;
05c0805b 430 wire [11:0] x, y;
92e851e1 431 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
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432 reg [5:0] slowctr = 0;
433 reg [7:0] colorcycle = 0;
434 wire [11:0] realx, realy;
435
436 wire logoenb;
437 wire [2:0] mandelr, mandelg, logor, logog;
438 wire [1:0] mandelb, logob;
439
05c0805b 440 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903 441 Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b
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442 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
443
444 assign {red,green,blue} =
445 border ? 8'b00000000 :
446 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
447
448 always @(posedge vs)
449 begin
450 if (rst)
451 begin
452 xofs <= -`XRES/2;
453 yofs <= -`YRES/2;
454 colorcycle <= 0;
455 end else begin
456 if (up) yofs <= yofs + 1;
457 else if (down) yofs <= yofs - 1;
458
459 if (left) xofs <= xofs + 1;
460 else if (right) xofs <= xofs - 1;
461
462 if (slowctr == 0)
463 colorcycle <= colorcycle + 1;
464 end
465
466 if (slowctr == 12)
467 slowctr <= 0;
468 else
469 slowctr <= slowctr + 1;
470 end
471endmodule
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