Potentially fixed triplepump: 75.028MHz, 4596 slices, 8537 LUTs, 1805 ffs
[mandelfpga.git] / Main.v
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cf1ae842 1/*
05c0805b
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2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
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12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
67 output reg [1:0] ovf);
68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x >> 1) : 0) +
74 (y[10] ? (x >> 2) : 0) +
75 (y[9] ? (x >> 3) : 0)) +
76 ((y[8] ? (x >> 4) : 0) +
77 (y[7] ? (x >> 5) : 0) +
78 (y[6] ? (x >> 6) : 0)))+
79 (((y[5] ? (x >> 7) : 0) +
80 (y[4] ? (x >> 8) : 0) +
81 (y[3] ? (x >> 9) : 0)) +
82 ((y[2] ? (x >> 10): 0) +
83 (y[1] ? (x >> 11): 0) +
84 (y[0] ? (x >> 12): 0)));
85 sign <= xsign ^ ysign;
86 end
87
88endmodule
89
90module Multiplier(
91 input clk,
92e851e1 92 input [12:0] x, y,
05c0805b 93 input xsign, ysign,
92e851e1 94 output wire [12:0] out,
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95 output wire sign,
96 output wire [1:0] overflow);
97
98 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
99
100endmodule
101
102module MandelUnit(
103 input clk,
104 input [12:0] x, y,
105 input xsign, ysign,
92e851e1 106 input [14:0] r, i,
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107 input rsign, isign,
108 input [7:0] ibail, icuriter,
109 output reg [12:0] xout, yout,
110 output reg xsout, ysout,
92e851e1 111 output reg [14:0] rout, iout,
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112 output reg rsout, isout,
113 output reg [7:0] obail, ocuriter);
114
92e851e1 115 wire [14:0] r2, i2, ri, diff;
9032b2b5 116 wire [15:0] twocdiff;
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117 wire r2sign, i2sign, risign, dsign;
118 wire [16:0] bigsum;
119 wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
120
121 reg [12:0] xd, yd;
122 reg rd, id;
123 reg xsd, ysd;
124 reg [7:0] ibaild, curiterd;
125
126 assign ri[0] = 0;
127
92e851e1
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128 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
129 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
130 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
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131
132 assign bigsum = r2 + i2;
133 assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
134 assign rin_ovf = rd;
135 assign iin_ovf = id;
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136 assign twocdiff = r2 - i2;
137 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
138 assign dsign = twocdiff[15];
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139
140 always @ (posedge clk)
141 begin
142 xd <= x;
143 yd <= y;
144 xsd <= xsign;
145 ysd <= ysign;
146 xout <= xd;
147 yout <= yd;
148 xsout <= xsd;
149 ysout <= ysd;
150 ibaild <= ibail;
151 curiterd <= icuriter;
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152 rd <= r[13] | r[14];
153 id <= i[13] | i[14];
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154
155 if (xsd ^ dsign) begin
156 if (diff > xd) begin
157 rout <= diff - xd;
158 rsout <= dsign;
159 end else begin
160 rout <= xd - diff;
161 rsout <= xsd;
162 end
163 end else begin
164 rout <= diff + xd;
165 rsout <= xsd;
166 end
167
168 if (ysd ^ risign) begin
169 if (ri > yd) begin
170 iout <= ri - yd;
171 isout <= risign;
172 end else begin
173 iout <= yd - ri;
174 isout <= ysd;
175 end
176 end else begin
177 iout <= ri + yd;
178 isout <= ysd;
179 end
180
181 // If we haven't bailed out, and we meet any of the bailout conditions,
182 // bail out now. Otherwise, leave the bailout at whatever it was before.
183 if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
184 obail <= curiterd;
185 else
186 obail <= ibaild;
187 ocuriter <= curiterd + 8'b1;
188 end
189
190endmodule
191
192module Mandelbrot(
193 input mclk,
194 input pixclk,
195 input [11:0] x, y,
92e851e1 196 input [13:0] xofs, yofs,
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197 input [7:0] colorofs,
198 input [2:0] scale,
199 output reg [2:0] red, green, output reg [1:0] blue);
281eac32 200
534b3903 201`define MAXOUTN 11
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202
203 wire [12:0] rx, ry;
204 wire [13:0] nx, ny;
205 wire rxsign, rysign;
206
207 assign nx = x + xofs;
208 assign ny = y + yofs;
209 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
210 assign rxsign = nx[13];
211 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
212 assign rysign = ny[13];
213
214
281eac32
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215 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
216 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
217 wire [7:0] mb[`MAXOUTN:0];
218 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
219 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
220 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 221
f802110e 222 wire [14:0] initx, inity, initr, initi;
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223 wire [7:0] initci, initb;
224 wire initxs, initys, initrs, initis;
225
534b3903
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226 // Values after the number of iterations denoted by the subscript.
227 reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
228 reg [7:0] stageci [2:1], stageb [2:1];
229 reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b 230
534b3903 231 reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b 232
534b3903
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233 assign initx = state[0] ? rx :
234 state[1] ? stagex[1] :
235 stagex[2];
236 assign inity = state[0] ? ry :
237 state[1] ? stagey[1] :
238 stagey[2];
239 assign initr = state[0] ? rx :
240 state[1] ? stager[1] :
241 stager[2];
242 assign initi = state[0] ? ry :
243 state[1] ? stagei[1] :
244 stagei[2];
245 assign initxs = state[0] ? rxsign :
246 state[1] ? stagexs[1] :
247 stagexs[2];
248 assign initys = state[0] ? rysign :
249 state[1] ? stageys[1] :
250 stageys[2];
251 assign initrs = state[0] ? rxsign :
252 state[1] ? stagers[1] :
253 stagers[2];
254 assign initis = state[0] ? rysign :
255 state[1] ? stageis[1] :
256 stageis[2];
257 assign initb = state[0] ? 8'b11111111 :
258 state[1] ? stageb[1] :
259 stageb[2];
260 assign initci = state[0] ? 8'b00000000 :
3068fa61
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261 state[1] ? stageci[1] :
262 stageci[2];
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263
264 reg [7:0] out;
534b3903
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265 reg typethea = 0; // Whether we have typed the A.
266 reg statekick = 0; // State needs to be kicked back to 3'b010 on the next mclk.
267
268 // This is guaranteed to converge after two pixclks.
269 //always @(negedge mclk)
270 // if (pixclk && !typethea) begin
271 // typethea <= 1;
272 // statekick <= 1;
273 // end else if (typethea) begin // This is the edge of the falling anus.
274 // typethea <= 0;
275 // statekick <= 0;
276 // end
05c0805b
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277
278 always @(posedge mclk)
279 begin
534b3903
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280 // Data output handling
281 if (state[0]) begin
05c0805b 282 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b 283 end
3068fa61 284 if (state[1]) begin
534b3903
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285 out <= ~mb[`MAXOUTN] + colorofs;
286 end
287
3068fa61 288 if (state[0]) begin // PnR0 in, PnR2 out
534b3903
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289 stagex[2] <= xprop[`MAXOUTN];
290 stagey[2] <= yprop[`MAXOUTN];
291 stager[2] <= mr[`MAXOUTN];
292 stagei[2] <= mi[`MAXOUTN];
293 stagexs[2] <= xsprop[`MAXOUTN];
294 stageys[2] <= ysprop[`MAXOUTN];
295 stagers[2] <= mrs[`MAXOUTN];
296 stageis[2] <= mis[`MAXOUTN];
297 stageb[2] <= mb[`MAXOUTN];
298 stageci[2] <= curiter[`MAXOUTN];
299 end
300
3068fa61 301 if (state[2]) begin // PnR2 in, PnR1 out
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302 stagex[1] <= xprop[`MAXOUTN];
303 stagey[1] <= yprop[`MAXOUTN];
304 stager[1] <= mr[`MAXOUTN];
305 stagei[1] <= mi[`MAXOUTN];
306 stagexs[1] <= xsprop[`MAXOUTN];
307 stageys[1] <= ysprop[`MAXOUTN];
308 stagers[1] <= mrs[`MAXOUTN];
309 stageis[1] <= mis[`MAXOUTN];
310 stageb[1] <= mb[`MAXOUTN];
311 stageci[1] <= curiter[`MAXOUTN];
312 end
313
314 if (statekick) // If a pixclk has happened, the state should be reset.
315 state <= 3'b010;
316 else // Otherwise, just poke it forward.
317 state <= {state[1], state[0], state[2]};
05c0805b
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318 end
319
320 MandelUnit mu0(
321 mclk,
322 initx, inity, initxs, initys,
323 initr, initi, initrs, initis,
324 initb, initci,
325 xprop[0], yprop[0], xsprop[0], ysprop[0],
326 mr[0], mi[0], mrs[0], mis[0],
327 mb[0], curiter[0]);
328
329 MandelUnit mu1(mclk,
330 xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
331 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
332 MandelUnit mu2(mclk,
333 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
334 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
335 MandelUnit mu3(mclk,
336 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
337 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
338 MandelUnit mu4(mclk,
339 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
340 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
341 MandelUnit mu5(mclk,
342 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
343 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
344 MandelUnit mu6(mclk,
345 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
346 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
347 MandelUnit mu7(mclk,
348 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
349 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
350 MandelUnit mu8(mclk,
351 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
352 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
353 MandelUnit mu9(mclk,
354 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
355 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
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356 MandelUnit mua(mclk,
357 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
358 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
359 MandelUnit mub(mclk,
360 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
361 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
281eac32 362
05c0805b
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363endmodule
364
365module Logo(
366 input pixclk,
367 input [11:0] x, y,
368 output wire enb,
369 output wire [2:0] red, green, output wire [1:0] blue);
370
371 reg [1:0] logo[8191:0];
372 initial $readmemb("logo.readmemb", logo);
373
374 assign enb = (x < 96) && (y < 64);
375 wire [12:0] addr = {y[5:0], x[6:0]};
376 wire [1:0] data = logo[addr];
377 assign {red, green, blue} =
378 (data == 2'b00) ? 8'b00000000 :
379 ((data == 2'b01) ? 8'b00011100 :
380 ((data == 2'b10) ? 8'b11100000 :
381 8'b11111111));
382endmodule
383
384module MandelTop(
385 input gclk, output wire dcmok,
386 output wire vs, hs,
387 output wire [2:0] red, green, output [1:0] blue,
388 input left, right, up, down, rst, cycle, logooff,
389 input [2:0] scale);
390
534b3903
JW
391
392 wire pixclk, mclk, gclk2, clk;
393 wire dcm1ok, dcm2ok;
394 assign dcmok = dcm1ok && dcm2ok;
395
396 IBUFG typeA(.O(clk), .I(gclk));
397
398 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
399 .CLKIN_IN(clk),
400 .CLKFX_OUT(pixclk),
401 .LOCKED_OUT(dcm1ok)
402 );
403
404 mandelDCM dcm2(
405 .CLKIN_IN(clk),
406 .CLKFX_OUT(mclk),
407 .LOCKED_OUT(dcm2ok)
408 );
409
05c0805b 410 wire border;
05c0805b 411 wire [11:0] x, y;
92e851e1 412 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b
JW
413 reg [5:0] slowctr = 0;
414 reg [7:0] colorcycle = 0;
415 wire [11:0] realx, realy;
416
417 wire logoenb;
418 wire [2:0] mandelr, mandelg, logor, logog;
419 wire [1:0] mandelb, logob;
420
534b3903 421
05c0805b
JW
422
423 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903 424 Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b
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425 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
426
427 assign {red,green,blue} =
428 border ? 8'b00000000 :
429 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
430
431 always @(posedge vs)
432 begin
433 if (rst)
434 begin
435 xofs <= -`XRES/2;
436 yofs <= -`YRES/2;
437 colorcycle <= 0;
438 end else begin
439 if (up) yofs <= yofs + 1;
440 else if (down) yofs <= yofs - 1;
441
442 if (left) xofs <= xofs + 1;
443 else if (right) xofs <= xofs - 1;
444
445 if (slowctr == 0)
446 colorcycle <= colorcycle + 1;
447 end
448
449 if (slowctr == 12)
450 slowctr <= 0;
451 else
452 slowctr <= slowctr + 1;
453 end
454endmodule
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