[mandelfpga.git] / Main.v

/*
 * MandelFPGA
 * by Joshua Wise and Chris Lu
 * 
 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
 * in real time on an FPGA.
 */

`define XRES 640
`define YRES 480
`define WHIRRRRR 21

module SyncGen(
	input pixclk,
	output reg vs, hs,
	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	output wire [11:0] xoutreal, youtreal,
	output reg border);
	
	reg [11:0] x = 0, y = 0;	// Used for generating border and timing.
	assign xoutreal = x;
	assign youtreal = y;
	
	parameter XFPORCH = 16;
	parameter XSYNC = 96;
	parameter XBPORCH = 48;
	
	parameter YFPORCH = 10;
	parameter YSYNC = 2;
	parameter YBPORCH = 29;

	always @(posedge pixclk)
	begin
		if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				y <= 0;
			else
				y <= y + 1;
			x <= 0;
		end else
			x <= x + 1;
			
		if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				yout <= 0;
			else
				yout <= yout + 1;
			xout <= 0;
		end else
			xout <= xout + 1;
		hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
		vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
		border <= (x > `XRES) || (y > `YRES);
	end
endmodule

// bits: 1.12

module NaiveMultiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output reg [12:0] out,
	output reg sign,
	output reg [1:0] ovf);

	always @(posedge clk)
	begin
		{ovf,out} <=
			(((y[12] ? (x     ) : 0)  +
			  (y[11] ? (x >> 1) : 0)  +
			  (y[10] ? (x >> 2) : 0)  +
			  (y[9]  ? (x >> 3) : 0)) +
			 ((y[8]  ? (x >> 4) : 0)  +
			  (y[7]  ? (x >> 5) : 0)  +
			  (y[6]  ? (x >> 6) : 0)))+
			(((y[5]  ? (x >> 7) : 0)  +
			  (y[4]  ? (x >> 8) : 0)  +
			  (y[3]  ? (x >> 9) : 0)) +
			 ((y[2]  ? (x >> 10): 0)  +
			  (y[1]  ? (x >> 11): 0)  +
			  (y[0]  ? (x >> 12): 0)));
		sign <= xsign ^ ysign;
	end

endmodule

module Multiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output wire [12:0] out,
	output wire sign,
	output wire [1:0] overflow);

	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);

endmodule

module MandelUnit(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	input [14:0] r, i,
	input rsign, isign,
	input [7:0] ibail, icuriter,
	output reg [12:0] xout, yout,
	output reg xsout, ysout,
	output reg [14:0] rout, iout,
	output reg rsout, isout,
	output reg [7:0] obail, ocuriter);

	wire [14:0] r2, i2, ri, diff;
	wire r2sign, i2sign, risign, dsign;
	wire [16:0] bigsum;
	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;

	reg [12:0] xd, yd;
	reg rd, id;
	reg xsd, ysd;
	reg [7:0] ibaild, curiterd;

	assign ri[0] = 0;

	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});

	assign bigsum = r2 + i2;
	assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
	assign rin_ovf = rd;
	assign iin_ovf = id;
	assign diff = (r2 > i2) ? r2 - i2 : i2 - r2;
	assign dsign = (r2 > i2) ? 0 : 1;

	always @ (posedge clk)
	begin
		xd <= x;
		yd <= y;
		xsd <= xsign;
		ysd <= ysign;
		xout <= xd;
		yout <= yd;
		xsout <= xsd;
		ysout <= ysd;
		ibaild <= ibail;
		curiterd <= icuriter;
		rd <= r[13] | r[14];
		id <= i[13] | i[14];

		if (xsd ^ dsign) begin
			if (diff > xd) begin
				rout <= diff - xd;
				rsout <= dsign;
			end else begin
				rout <= xd - diff;
				rsout <= xsd;
			end
		end else begin
			rout <= diff + xd;
			rsout <= xsd;
		end
		
		if (ysd ^ risign) begin
			if (ri > yd) begin
				iout <= ri - yd;
				isout <= risign;
			end else begin
				iout <= yd - ri;
				isout <= ysd;
			end
		end else begin
			iout <= ri + yd;
			isout <= ysd;
		end
		
		// If we haven't bailed out, and we meet any of the bailout conditions,
		// bail out now.  Otherwise, leave the bailout at whatever it was before.
		if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
			obail <= curiterd;
		else
			obail <= ibaild;
		ocuriter <= curiterd + 8'b1;
	end

endmodule

module Mandelbrot(
	input mclk,
	input pixclk,
	input [11:0] x, y,
	input [13:0] xofs, yofs,
	input [7:0] colorofs,
	input [2:0] scale,
	output reg [2:0] red, green, output reg [1:0] blue);
	
	wire [12:0] rx, ry;
	wire [13:0] nx, ny;
	wire rxsign, rysign;
	
	assign nx = x + xofs;
	assign ny = y + yofs;
	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	assign rxsign = nx[13];
	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	assign rysign = ny[13];
	

	wire [14:0] mr[9:0], mi[9:0];
	wire mrs[9:0], mis[9:0];
	wire [7:0] mb[9:0];
	wire [12:0] xprop[9:0], yprop[9:0];
	wire xsprop[9:0], ysprop[9:0];
	wire [7:0] curiter[9:0];
	
	wire [14:0] initx, inity, initr, initi;
	wire [7:0] initci, initb;
	wire initxs, initys, initrs, initis;
	
	reg [14:0] loopx, loopy, loopr, loopi;
	reg [7:0] loopci, loopb;
	reg loopxs, loopys, looprs, loopis;
	
	reg state = 0;
	
	// On pixclk = 1,
	//    A new value to be loaded comes in, and a value in need of loopback comes out.
	// On pixclk = 0,
	//    A new value in need of loopback comes in, and a completed value comes out.
	
	assign initx = state ? rx : loopx;
	assign inity = state ? ry : loopy;
	assign initr = state ? rx : loopr;
	assign initi = state ? ry : loopi;
	assign initxs = state ? rxsign : loopxs;
	assign initys = state ? rysign : loopys;
	assign initrs = state ? rxsign : looprs;
	assign initis = state ? rysign : loopis;
	assign initb = state ? 8'b11111111 : loopb;
	assign initci = state ? 8'b00000000 : loopci;
	
	reg [7:0] out;
	reg pixclksync;
	always @(negedge mclk)
		pixclksync <= ~pixclk;
	
	always @(posedge mclk)
	begin
		if (!state) begin
			out <= ~mb[9] + colorofs;
		end else begin
			{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
			loopx <= xprop[9];
			loopy <= yprop[9];
			loopr <= mr[9];
			loopi <= mi[9];
			loopxs <= xsprop[9];
			loopys <= ysprop[9];
			looprs <= mrs[9];
			loopis <= mis[9];
			loopb <= mb[9];
			loopci <= curiter[9];
		end
		state <= ~pixclksync;
	end

	MandelUnit mu0(
		mclk,
		initx, inity, initxs, initys,
		initr, initi, initrs, initis,
		initb, initci,
		xprop[0], yprop[0], xsprop[0], ysprop[0],
		mr[0], mi[0], mrs[0], mis[0],
		mb[0], curiter[0]);

	MandelUnit mu1(mclk,
		xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
		xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
	MandelUnit mu2(mclk,
		xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
		xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
	MandelUnit mu3(mclk,
		xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
		xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
	MandelUnit mu4(mclk,
		xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
		xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
	MandelUnit mu5(mclk,
		xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
		xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
	MandelUnit mu6(mclk,
		xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
		xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
	MandelUnit mu7(mclk,
		xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
		xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
	MandelUnit mu8(mclk,
		xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
		xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
	MandelUnit mu9(mclk,
		xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
		xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
	
endmodule

module Logo(
	input pixclk,
	input [11:0] x, y,
	output wire enb,
	output wire [2:0] red, green, output wire [1:0] blue);
	
	reg [1:0] logo[8191:0];
	initial $readmemb("logo.readmemb", logo);
	
	assign enb = (x < 96) && (y < 64);
	wire [12:0] addr = {y[5:0], x[6:0]};
	wire [1:0] data = logo[addr];
	assign {red, green, blue} = 
		 (data == 2'b00) ? 8'b00000000 :
		((data == 2'b01) ? 8'b00011100 :
		((data == 2'b10) ? 8'b11100000 :
		                    8'b11111111));
endmodule

module MandelTop(
	input gclk, output wire dcmok,
	output wire vs, hs,
	output wire [2:0] red, green, output [1:0] blue,
	input left, right, up, down, rst, cycle, logooff,
	input [2:0] scale);

	wire border;
	wire pixclk;
	wire [7:0] zero = 8'b0;
	wire clk;
	wire [11:0] x, y;
	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
	reg [5:0] slowctr = 0;
	reg [7:0] colorcycle = 0;
	wire [11:0] realx, realy;
	
	wire logoenb;
	wire [2:0] mandelr, mandelg, logor, logog;
	wire [1:0] mandelb, logob;
	
	pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
		.CLKIN_IN(gclk), 
		.CLKFX_OUT(pixclk),
		.CLKIN_IBUFG_OUT(clk),
		.LOCKED_OUT(dcmok)
		);

	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
	Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	
	assign {red,green,blue} =
		border ? 8'b00000000 :
		(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	
	always @(posedge vs)
	begin
		if (rst)
		begin
			xofs <= -`XRES/2;
			yofs <= -`YRES/2;
			colorcycle <= 0;
		end else begin
			if (up) yofs <= yofs + 1;
			else if (down) yofs <= yofs - 1;
			
			if (left) xofs <= xofs + 1;
			else if (right) xofs <= xofs - 1;
			
			if (slowctr == 0)
				colorcycle <= colorcycle + 1;
		end
		
		if (slowctr == 12)
			slowctr <= 0;
		else
			slowctr <= slowctr + 1;
	end
endmodule
Commit	Line	Data
05c0805b JW	1	/*
	2	* MandelFPGA
	3	* by Joshua Wise and Chris Lu
	4	*
	5	* An implementation of a pipelined algorithm to calculate the Mandelbrot set
	6	* in real time on an FPGA.
	7	*/
	8
	9	`define XRES 640
	10	`define YRES 480
	11	`define WHIRRRRR 21
	12
	13	module SyncGen(
	14	input pixclk,
	15	output reg vs, hs,
	16	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	17	output wire [11:0] xoutreal, youtreal,
	18	output reg border);
	19
	20	reg [11:0] x = 0, y = 0; // Used for generating border and timing.
	21	assign xoutreal = x;
	22	assign youtreal = y;
	23
	24	parameter XFPORCH = 16;
	25	parameter XSYNC = 96;
	26	parameter XBPORCH = 48;
	27
	28	parameter YFPORCH = 10;
	29	parameter YSYNC = 2;
	30	parameter YBPORCH = 29;
	31
	32	always @(posedge pixclk)
	33	begin
	34	if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	35	begin
	36	if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	37	y <= 0;
	38	else
	39	y <= y + 1;
	40	x <= 0;
	41	end else
	42	x <= x + 1;
	43
	44	if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	45	begin
	46	if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	47	yout <= 0;
	48	else
	49	yout <= yout + 1;
	50	xout <= 0;
	51	end else
	52	xout <= xout + 1;
	53	hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
	54	vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
	55	border <= (x > `XRES) \|\| (y > `YRES);
	56	end
	57	endmodule
	58
	59	// bits: 1.12
	60
	61	module NaiveMultiplier(
	62	input clk,
	63	input [12:0] x, y,
	64	input xsign, ysign,
65	output reg [12:0] out,
66	output reg sign,
67	output reg [1:0] ovf);
68
69	always @(posedge clk)
70	begin
71	{ovf,out} <=
72	(((y[12] ? (x ) : 0) +
73	(y[11] ? (x >> 1) : 0) +
74	(y[10] ? (x >> 2) : 0) +
75	(y[9] ? (x >> 3) : 0)) +
76	((y[8] ? (x >> 4) : 0) +
77	(y[7] ? (x >> 5) : 0) +
78	(y[6] ? (x >> 6) : 0)))+
79	(((y[5] ? (x >> 7) : 0) +
80	(y[4] ? (x >> 8) : 0) +
81	(y[3] ? (x >> 9) : 0)) +
82	((y[2] ? (x >> 10): 0) +
83	(y[1] ? (x >> 11): 0) +
84	(y[0] ? (x >> 12): 0)));
85	sign <= xsign ^ ysign;
86	end
87
88	endmodule
89
90	module Multiplier(
91	input clk,
92e851e1	92	input [12:0] x, y,
05c0805b	93	input xsign, ysign,
92e851e1	94	output wire [12:0] out,
05c0805b JW	95	output wire sign,
	96	output wire [1:0] overflow);
	97
	98	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
	99
	100	endmodule
	101
	102	module MandelUnit(
	103	input clk,
	104	input [12:0] x, y,
	105	input xsign, ysign,
92e851e1	106	input [14:0] r, i,
05c0805b JW	107	input rsign, isign,
	108	input [7:0] ibail, icuriter,
	109	output reg [12:0] xout, yout,
	110	output reg xsout, ysout,
92e851e1	111	output reg [14:0] rout, iout,
05c0805b JW	112	output reg rsout, isout,
	113	output reg [7:0] obail, ocuriter);
	114
92e851e1	115	wire [14:0] r2, i2, ri, diff;
05c0805b JW	116	wire r2sign, i2sign, risign, dsign;
	117	wire [16:0] bigsum;
	118	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
	119
	120	reg [12:0] xd, yd;
	121	reg rd, id;
	122	reg xsd, ysd;
	123	reg [7:0] ibaild, curiterd;
	124
	125	assign ri[0] = 0;
	126
92e851e1 JW	127	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
	128	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
	129	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
05c0805b JW	130
	131	assign bigsum = r2 + i2;
	132	assign bigsum_ovf = bigsum[16] \| bigsum[15] \| bigsum[14];
	133	assign rin_ovf = rd;
	134	assign iin_ovf = id;
	135	assign diff = (r2 > i2) ? r2 - i2 : i2 - r2;
	136	assign dsign = (r2 > i2) ? 0 : 1;
	137
	138	always @ (posedge clk)
	139	begin
	140	xd <= x;
	141	yd <= y;
	142	xsd <= xsign;
	143	ysd <= ysign;
	144	xout <= xd;
	145	yout <= yd;
	146	xsout <= xsd;
	147	ysout <= ysd;
	148	ibaild <= ibail;
	149	curiterd <= icuriter;
92e851e1 JW	150	rd <= r[13] \| r[14];
92e851e1 JW	151	id <= i[13] \| i[14];
05c0805b JW	152
	153	if (xsd ^ dsign) begin
	154	if (diff > xd) begin
	155	rout <= diff - xd;
	156	rsout <= dsign;
	157	end else begin
	158	rout <= xd - diff;
	159	rsout <= xsd;
	160	end
	161	end else begin
	162	rout <= diff + xd;
	163	rsout <= xsd;
	164	end
	165
	166	if (ysd ^ risign) begin
	167	if (ri > yd) begin
	168	iout <= ri - yd;
	169	isout <= risign;
	170	end else begin
	171	iout <= yd - ri;
	172	isout <= ysd;
	173	end
	174	end else begin
	175	iout <= ri + yd;
	176	isout <= ysd;
	177	end
	178
	179	// If we haven't bailed out, and we meet any of the bailout conditions,
	180	// bail out now. Otherwise, leave the bailout at whatever it was before.
	181	if ((ibaild == 255) && (bigsum_ovf \| rin_ovf \| iin_ovf))
	182	obail <= curiterd;
	183	else
	184	obail <= ibaild;
	185	ocuriter <= curiterd + 8'b1;
	186	end
	187
	188	endmodule
	189
	190	module Mandelbrot(
	191	input mclk,
	192	input pixclk,
	193	input [11:0] x, y,
92e851e1	194	input [13:0] xofs, yofs,
05c0805b JW	195	input [7:0] colorofs,
	196	input [2:0] scale,
	197	output reg [2:0] red, green, output reg [1:0] blue);
	198
	199	wire [12:0] rx, ry;
	200	wire [13:0] nx, ny;
	201	wire rxsign, rysign;
	202
	203	assign nx = x + xofs;
	204	assign ny = y + yofs;
	205	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	206	assign rxsign = nx[13];
	207	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	208	assign rysign = ny[13];
	209
	210
92e851e1	211	wire [14:0] mr[9:0], mi[9:0];
05c0805b JW	212	wire mrs[9:0], mis[9:0];
	213	wire [7:0] mb[9:0];
	214	wire [12:0] xprop[9:0], yprop[9:0];
	215	wire xsprop[9:0], ysprop[9:0];
	216	wire [7:0] curiter[9:0];
	217
f802110e	218	wire [14:0] initx, inity, initr, initi;
05c0805b JW	219	wire [7:0] initci, initb;
	220	wire initxs, initys, initrs, initis;
	221
92e851e1	222	reg [14:0] loopx, loopy, loopr, loopi;
05c0805b JW	223	reg [7:0] loopci, loopb;
	224	reg loopxs, loopys, looprs, loopis;
	225
	226	reg state = 0;
	227
	228	// On pixclk = 1,
	229	// A new value to be loaded comes in, and a value in need of loopback comes out.
	230	// On pixclk = 0,
	231	// A new value in need of loopback comes in, and a completed value comes out.
	232
	233	assign initx = state ? rx : loopx;
	234	assign inity = state ? ry : loopy;
	235	assign initr = state ? rx : loopr;
	236	assign initi = state ? ry : loopi;
	237	assign initxs = state ? rxsign : loopxs;
	238	assign initys = state ? rysign : loopys;
	239	assign initrs = state ? rxsign : looprs;
	240	assign initis = state ? rysign : loopis;
	241	assign initb = state ? 8'b11111111 : loopb;
	242	assign initci = state ? 8'b00000000 : loopci;
	243
	244	reg [7:0] out;
	245	reg pixclksync;
	246	always @(negedge mclk)
	247	pixclksync <= ~pixclk;
	248
	249	always @(posedge mclk)
	250	begin
	251	if (!state) begin
	252	out <= ~mb[9] + colorofs;
	253	end else begin
	254	{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
	255	loopx <= xprop[9];
	256	loopy <= yprop[9];
	257	loopr <= mr[9];
	258	loopi <= mi[9];
	259	loopxs <= xsprop[9];
	260	loopys <= ysprop[9];
	261	looprs <= mrs[9];
	262	loopis <= mis[9];
	263	loopb <= mb[9];
	264	loopci <= curiter[9];
	265	end
	266	state <= ~pixclksync;
	267	end
	268
	269	MandelUnit mu0(
	270	mclk,
	271	initx, inity, initxs, initys,
	272	initr, initi, initrs, initis,
	273	initb, initci,
	274	xprop[0], yprop[0], xsprop[0], ysprop[0],
	275	mr[0], mi[0], mrs[0], mis[0],
	276	mb[0], curiter[0]);
	277
	278	MandelUnit mu1(mclk,
	279	xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
	280	xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
	281	MandelUnit mu2(mclk,
	282	xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
	283	xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
	284	MandelUnit mu3(mclk,
	285	xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
	286	xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
287	MandelUnit mu4(mclk,
288	xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
289	xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
290	MandelUnit mu5(mclk,
291	xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
292	xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
293	MandelUnit mu6(mclk,
294	xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
295	xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
296	MandelUnit mu7(mclk,
297	xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
298	xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
299	MandelUnit mu8(mclk,
300	xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
301	xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
302	MandelUnit mu9(mclk,
303	xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
304	xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
305
306	endmodule
307
308	module Logo(
309	input pixclk,
310	input [11:0] x, y,
311	output wire enb,
312	output wire [2:0] red, green, output wire [1:0] blue);
313
314	reg [1:0] logo[8191:0];
315	initial $readmemb("logo.readmemb", logo);
316
317	assign enb = (x < 96) && (y < 64);
318	wire [12:0] addr = {y[5:0], x[6:0]};
319	wire [1:0] data = logo[addr];
320	assign {red, green, blue} =
321	(data == 2'b00) ? 8'b00000000 :
322	((data == 2'b01) ? 8'b00011100 :
323	((data == 2'b10) ? 8'b11100000 :
324	8'b11111111));
325	endmodule
326
327	module MandelTop(
328	input gclk, output wire dcmok,
329	output wire vs, hs,
330	output wire [2:0] red, green, output [1:0] blue,
331	input left, right, up, down, rst, cycle, logooff,
332	input [2:0] scale);
333
334	wire border;
335	wire pixclk;
336	wire [7:0] zero = 8'b0;
337	wire clk;
338	wire [11:0] x, y;
92e851e1	339	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b JW	340	reg [5:0] slowctr = 0;
	341	reg [7:0] colorcycle = 0;
	342	wire [11:0] realx, realy;
	343
	344	wire logoenb;
	345	wire [2:0] mandelr, mandelg, logor, logog;
	346	wire [1:0] mandelb, logob;
	347
	348	pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
	349	.CLKIN_IN(gclk),
	350	.CLKFX_OUT(pixclk),
	351	.CLKIN_IBUFG_OUT(clk),
	352	.LOCKED_OUT(dcmok)
	353	);
	354
	355	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
	356	Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
	357	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	358
	359	assign {red,green,blue} =
	360	border ? 8'b00000000 :
	361	(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	362
	363	always @(posedge vs)
	364	begin
	365	if (rst)
	366	begin
	367	xofs <= -`XRES/2;
	368	yofs <= -`YRES/2;
	369	colorcycle <= 0;
	370	end else begin
	371	if (up) yofs <= yofs + 1;
	372	else if (down) yofs <= yofs - 1;
	373
	374	if (left) xofs <= xofs + 1;
	375	else if (right) xofs <= xofs - 1;
	376
	377	if (slowctr == 0)
	378	colorcycle <= colorcycle + 1;
	379	end
	380
	381	if (slowctr == 12)
	382	slowctr <= 0;
	383	else
	384	slowctr <= slowctr + 1;
	385	end
	386	endmodule