Reg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.
[mandelfpga.git] / Main.v
CommitLineData
cf1ae842 1/*
05c0805b
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2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
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12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
fb8d158b 67 output reg ovf);
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68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x >> 1) : 0) +
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74 (y[10] ? (x >> 2) : 0)) +
75 (((y[9] ? (x >> 3) : 0) +
76 (y[8] ? (x >> 4) : 0))+
77 ((y[7] ? (x >> 5) : 0) +
78 (y[6] ? (x >> 6) : 0))))+
79
05c0805b 80 (((y[5] ? (x >> 7) : 0) +
fb8d158b 81 (y[4] ? (x >> 8) : 0)+
05c0805b 82 (y[3] ? (x >> 9) : 0)) +
fb8d158b 83 ((y[2] ? (x >> 10): 0) +
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84 (y[1] ? (x >> 11): 0) +
85 (y[0] ? (x >> 12): 0)));
86 sign <= xsign ^ ysign;
87 end
88
89endmodule
90
91module Multiplier(
92 input clk,
92e851e1 93 input [12:0] x, y,
05c0805b 94 input xsign, ysign,
92e851e1 95 output wire [12:0] out,
05c0805b 96 output wire sign,
fb8d158b 97 output wire overflow);
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98
99 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
100
101endmodule
102
fb8d158b 103// Yuq.
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104module MandelUnit(
105 input clk,
106 input [12:0] x, y,
107 input xsign, ysign,
92e851e1 108 input [14:0] r, i,
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109 input rsign, isign,
110 input [7:0] ibail, icuriter,
111 output reg [12:0] xout, yout,
112 output reg xsout, ysout,
92e851e1 113 output reg [14:0] rout, iout,
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114 output reg rsout, isout,
115 output reg [7:0] obail, ocuriter);
116
92e851e1 117 wire [14:0] r2, i2, ri, diff;
9032b2b5 118 wire [15:0] twocdiff;
05c0805b 119 wire r2sign, i2sign, risign, dsign;
a3a4354b 120 wire [15:0] bigsum;
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121 wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
122
123 reg [12:0] xd, yd;
124 reg rd, id;
125 reg xsd, ysd;
126 reg [7:0] ibaild, curiterd;
127
128 assign ri[0] = 0;
129
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130 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
131 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
132 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
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133
134 assign bigsum = r2 + i2;
a3a4354b 135 assign bigsum_ovf = bigsum[15] | bigsum[14];
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136 assign rin_ovf = rd;
137 assign iin_ovf = id;
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138 assign twocdiff = r2 - i2;
139 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
140 assign dsign = twocdiff[15];
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141
142 always @ (posedge clk)
143 begin
144 xd <= x;
145 yd <= y;
146 xsd <= xsign;
147 ysd <= ysign;
148 xout <= xd;
149 yout <= yd;
150 xsout <= xsd;
151 ysout <= ysd;
152 ibaild <= ibail;
153 curiterd <= icuriter;
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154 rd <= r[13] | r[14];
155 id <= i[13] | i[14];
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156
157 if (xsd ^ dsign) begin
158 if (diff > xd) begin
159 rout <= diff - xd;
160 rsout <= dsign;
161 end else begin
162 rout <= xd - diff;
163 rsout <= xsd;
164 end
165 end else begin
166 rout <= diff + xd;
167 rsout <= xsd;
168 end
169
170 if (ysd ^ risign) begin
171 if (ri > yd) begin
172 iout <= ri - yd;
173 isout <= risign;
174 end else begin
175 iout <= yd - ri;
176 isout <= ysd;
177 end
178 end else begin
179 iout <= ri + yd;
180 isout <= ysd;
181 end
182
183 // If we haven't bailed out, and we meet any of the bailout conditions,
184 // bail out now. Otherwise, leave the bailout at whatever it was before.
185 if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
186 obail <= curiterd;
187 else
188 obail <= ibaild;
189 ocuriter <= curiterd + 8'b1;
190 end
191
192endmodule
193
194module Mandelbrot(
195 input mclk,
196 input pixclk,
197 input [11:0] x, y,
92e851e1 198 input [13:0] xofs, yofs,
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199 input [7:0] colorofs,
200 input [2:0] scale,
201 output reg [2:0] red, green, output reg [1:0] blue);
281eac32 202
534b3903 203`define MAXOUTN 11
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204
205 wire [12:0] rx, ry;
206 wire [13:0] nx, ny;
207 wire rxsign, rysign;
208
209 assign nx = x + xofs;
210 assign ny = y + yofs;
211 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
212 assign rxsign = nx[13];
213 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
214 assign rysign = ny[13];
05c0805b 215
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216 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
217 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
218 wire [7:0] mb[`MAXOUTN:0];
219 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
220 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
221 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 222
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223 reg [14:0] initx, inity, initr, initi;
224 reg [7:0] initci, initb;
225 reg initxs, initys, initrs, initis;
05c0805b 226
534b3903
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227 // Values after the number of iterations denoted by the subscript.
228 reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
229 reg [7:0] stageci [2:1], stageb [2:1];
230 reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b 231
534b3903 232 reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b 233
79af494a
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234 // States are advanced one from what they should be, so that they'll
235 // get there on the _next_ mclk.
236 always @(posedge mclk)
237 begin
238 initx <= (state[2]) ? rx :
239 (state[0]) ? stagex[1] :
240 (state[1]) ? stagex[2] : 0;
241 inity <= (state[2]) ? ry :
242 (state[0]) ? stagey[1] :
243 (state[1]) ? stagey[2] : 0;
244 initr <= (state[2]) ? rx :
245 (state[0]) ? stager[1] :
246 (state[1]) ? stager[2] : 0;
247 initi <= (state[2]) ? ry :
248 (state[0]) ? stagei[1] :
249 (state[1]) ? stagei[2] : 0;
250 initxs <= (state[2]) ? rxsign :
251 (state[0]) ? stagexs[1] :
252 (state[1]) ? stagexs[2] : 0;
253 initys <= (state[2]) ? rysign :
254 (state[0]) ? stageys[1] :
255 (state[1]) ? stageys[2] : 0;
256 initrs <= (state[2]) ? rxsign :
257 (state[0]) ? stagers[1] :
258 (state[1]) ? stagers[2] : 0;
259 initis <= (state[2]) ? rysign :
260 (state[0]) ? stageis[1] :
261 (state[1]) ? stageis[2] : 0;
262 initb <= (state[2]) ? 8'b11111111 :
263 (state[0]) ? stageb[1] :
264 (state[1]) ? stageb[2] : 0;
265 initci <= (state[2]) ? 8'b00000000 :
266 (state[0]) ? stageci[1] :
267 (state[1]) ? stageci[2] : 0;
268 end
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269
270 reg [7:0] out;
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271
272 // We detect when the state should be poked by a high negedge followed
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273 // by a high posedge -- if that happens, then we're guaranteed that the
274 // state following the current state will be 3'b100.
251788d8 275 reg lastneg;
265061f2 276 always @(negedge mclk)
251788d8 277 lastneg <= pixclk;
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278
279 always @(posedge mclk)
280 begin
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281 if (lastneg && pixclk) // If a pixclk has happened, the state should be reset.
282 state <= 3'b100;
283 else // Otherwise, just poke it forward.
a3a4354b
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284 case(state)
285 3'b001: state <= 3'b010;
286 3'b010: state <= 3'b100;
287 3'b100: state <= 3'b001;
288 endcase
251788d8 289
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290 // Data output handling
291 if (state[0]) begin
05c0805b 292 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b 293 end
3068fa61 294 if (state[1]) begin
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295 out <= ~mb[`MAXOUTN] + colorofs;
296 end
297
3068fa61 298 if (state[0]) begin // PnR0 in, PnR2 out
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299 stagex[2] <= xprop[`MAXOUTN];
300 stagey[2] <= yprop[`MAXOUTN];
301 stager[2] <= mr[`MAXOUTN];
302 stagei[2] <= mi[`MAXOUTN];
303 stagexs[2] <= xsprop[`MAXOUTN];
304 stageys[2] <= ysprop[`MAXOUTN];
305 stagers[2] <= mrs[`MAXOUTN];
306 stageis[2] <= mis[`MAXOUTN];
307 stageb[2] <= mb[`MAXOUTN];
308 stageci[2] <= curiter[`MAXOUTN];
309 end
310
3068fa61 311 if (state[2]) begin // PnR2 in, PnR1 out
534b3903
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312 stagex[1] <= xprop[`MAXOUTN];
313 stagey[1] <= yprop[`MAXOUTN];
314 stager[1] <= mr[`MAXOUTN];
315 stagei[1] <= mi[`MAXOUTN];
316 stagexs[1] <= xsprop[`MAXOUTN];
317 stageys[1] <= ysprop[`MAXOUTN];
318 stagers[1] <= mrs[`MAXOUTN];
319 stageis[1] <= mis[`MAXOUTN];
320 stageb[1] <= mb[`MAXOUTN];
321 stageci[1] <= curiter[`MAXOUTN];
322 end
05c0805b
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323 end
324
325 MandelUnit mu0(
326 mclk,
327 initx, inity, initxs, initys,
328 initr, initi, initrs, initis,
329 initb, initci,
330 xprop[0], yprop[0], xsprop[0], ysprop[0],
331 mr[0], mi[0], mrs[0], mis[0],
332 mb[0], curiter[0]);
333
334 MandelUnit mu1(mclk,
335 xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
336 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
337 MandelUnit mu2(mclk,
338 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
339 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
340 MandelUnit mu3(mclk,
341 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
342 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
343 MandelUnit mu4(mclk,
344 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
345 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
346 MandelUnit mu5(mclk,
347 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
348 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
349 MandelUnit mu6(mclk,
350 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
351 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
352 MandelUnit mu7(mclk,
353 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
354 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
355 MandelUnit mu8(mclk,
356 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
357 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
358 MandelUnit mu9(mclk,
359 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
360 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
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361 MandelUnit mua(mclk,
362 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
363 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
364 MandelUnit mub(mclk,
365 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
366 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
281eac32 367
05c0805b
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368endmodule
369
370module Logo(
371 input pixclk,
372 input [11:0] x, y,
373 output wire enb,
374 output wire [2:0] red, green, output wire [1:0] blue);
375
376 reg [1:0] logo[8191:0];
377 initial $readmemb("logo.readmemb", logo);
378
379 assign enb = (x < 96) && (y < 64);
380 wire [12:0] addr = {y[5:0], x[6:0]};
381 wire [1:0] data = logo[addr];
382 assign {red, green, blue} =
383 (data == 2'b00) ? 8'b00000000 :
384 ((data == 2'b01) ? 8'b00011100 :
385 ((data == 2'b10) ? 8'b11100000 :
386 8'b11111111));
387endmodule
388
389module MandelTop(
390 input gclk, output wire dcmok,
391 output wire vs, hs,
392 output wire [2:0] red, green, output [1:0] blue,
393 input left, right, up, down, rst, cycle, logooff,
394 input [2:0] scale);
395
534b3903
JW
396
397 wire pixclk, mclk, gclk2, clk;
398 wire dcm1ok, dcm2ok;
c3ed4329 399 assign dcmok = dcm1ok && dcm2ok;
265061f2 400
c3ed4329 401 IBUFG typeA(.O(clk), .I(gclk));
534b3903 402
c3ed4329
JW
403 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
404 .CLKIN_IN(clk),
405 .CLKFX_OUT(pixclk),
406 .LOCKED_OUT(dcm1ok)
407 );
534b3903 408
c3ed4329
JW
409 mandelDCM dcm2(
410 .CLKIN_IN(clk),
411 .CLKFX_OUT(mclk),
412 .LOCKED_OUT(dcm2ok)
413 );
534b3903 414
05c0805b 415 wire border;
05c0805b 416 wire [11:0] x, y;
92e851e1 417 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b
JW
418 reg [5:0] slowctr = 0;
419 reg [7:0] colorcycle = 0;
420 wire [11:0] realx, realy;
421
422 wire logoenb;
423 wire [2:0] mandelr, mandelg, logor, logog;
424 wire [1:0] mandelb, logob;
425
534b3903 426
05c0805b
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427
428 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903 429 Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b
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430 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
431
432 assign {red,green,blue} =
433 border ? 8'b00000000 :
434 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
435
436 always @(posedge vs)
437 begin
438 if (rst)
439 begin
440 xofs <= -`XRES/2;
441 yofs <= -`YRES/2;
442 colorcycle <= 0;
443 end else begin
444 if (up) yofs <= yofs + 1;
445 else if (down) yofs <= yofs - 1;
446
447 if (left) xofs <= xofs + 1;
448 else if (right) xofs <= xofs - 1;
449
450 if (slowctr == 0)
451 colorcycle <= colorcycle + 1;
452 end
453
454 if (slowctr == 12)
455 slowctr <= 0;
456 else
457 slowctr <= slowctr + 1;
458 end
459endmodule
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