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[mandelfpga.git] / Main.v
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cf1ae842 1/*
05c0805b
JW
2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
JW
12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
fb8d158b 67 output reg ovf);
05c0805b
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68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x >> 1) : 0) +
fb8d158b
JW
74 (y[10] ? (x >> 2) : 0)) +
75 (((y[9] ? (x >> 3) : 0) +
76 (y[8] ? (x >> 4) : 0))+
77 ((y[7] ? (x >> 5) : 0) +
78 (y[6] ? (x >> 6) : 0))))+
79
05c0805b 80 (((y[5] ? (x >> 7) : 0) +
fb8d158b 81 (y[4] ? (x >> 8) : 0)+
05c0805b 82 (y[3] ? (x >> 9) : 0)) +
fb8d158b 83 ((y[2] ? (x >> 10): 0) +
05c0805b
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84 (y[1] ? (x >> 11): 0) +
85 (y[0] ? (x >> 12): 0)));
86 sign <= xsign ^ ysign;
87 end
88
89endmodule
90
91module Multiplier(
92 input clk,
92e851e1 93 input [12:0] x, y,
05c0805b 94 input xsign, ysign,
92e851e1 95 output wire [12:0] out,
05c0805b 96 output wire sign,
fb8d158b 97 output wire overflow);
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98
99 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
100
101endmodule
102
fb8d158b 103// Yuq.
05c0805b
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104module MandelUnit(
105 input clk,
106 input [12:0] x, y,
107 input xsign, ysign,
92e851e1 108 input [14:0] r, i,
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109 input rsign, isign,
110 input [7:0] ibail, icuriter,
111 output reg [12:0] xout, yout,
112 output reg xsout, ysout,
92e851e1 113 output reg [14:0] rout, iout,
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114 output reg rsout, isout,
115 output reg [7:0] obail, ocuriter);
116
92e851e1 117 wire [14:0] r2, i2, ri, diff;
9032b2b5 118 wire [15:0] twocdiff;
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119 wire r2sign, i2sign, risign, dsign;
120 wire [16:0] bigsum;
121 wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
122
123 reg [12:0] xd, yd;
124 reg rd, id;
125 reg xsd, ysd;
126 reg [7:0] ibaild, curiterd;
127
128 assign ri[0] = 0;
129
92e851e1
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130 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
131 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
132 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
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133
134 assign bigsum = r2 + i2;
135 assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
136 assign rin_ovf = rd;
137 assign iin_ovf = id;
9032b2b5
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138 assign twocdiff = r2 - i2;
139 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
140 assign dsign = twocdiff[15];
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141
142 always @ (posedge clk)
143 begin
144 xd <= x;
145 yd <= y;
146 xsd <= xsign;
147 ysd <= ysign;
148 xout <= xd;
149 yout <= yd;
150 xsout <= xsd;
151 ysout <= ysd;
152 ibaild <= ibail;
153 curiterd <= icuriter;
92e851e1
JW
154 rd <= r[13] | r[14];
155 id <= i[13] | i[14];
05c0805b
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156
157 if (xsd ^ dsign) begin
158 if (diff > xd) begin
159 rout <= diff - xd;
160 rsout <= dsign;
161 end else begin
162 rout <= xd - diff;
163 rsout <= xsd;
164 end
165 end else begin
166 rout <= diff + xd;
167 rsout <= xsd;
168 end
169
170 if (ysd ^ risign) begin
171 if (ri > yd) begin
172 iout <= ri - yd;
173 isout <= risign;
174 end else begin
175 iout <= yd - ri;
176 isout <= ysd;
177 end
178 end else begin
179 iout <= ri + yd;
180 isout <= ysd;
181 end
182
183 // If we haven't bailed out, and we meet any of the bailout conditions,
184 // bail out now. Otherwise, leave the bailout at whatever it was before.
185 if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
186 obail <= curiterd;
187 else
188 obail <= ibaild;
189 ocuriter <= curiterd + 8'b1;
190 end
191
192endmodule
193
194module Mandelbrot(
195 input mclk,
196 input pixclk,
197 input [11:0] x, y,
92e851e1 198 input [13:0] xofs, yofs,
05c0805b
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199 input [7:0] colorofs,
200 input [2:0] scale,
201 output reg [2:0] red, green, output reg [1:0] blue);
281eac32 202
534b3903 203`define MAXOUTN 11
05c0805b
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204
205 wire [12:0] rx, ry;
206 wire [13:0] nx, ny;
207 wire rxsign, rysign;
208
209 assign nx = x + xofs;
210 assign ny = y + yofs;
211 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
212 assign rxsign = nx[13];
213 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
214 assign rysign = ny[13];
215
216
281eac32
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217 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
218 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
219 wire [7:0] mb[`MAXOUTN:0];
220 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
221 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
222 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 223
f802110e 224 wire [14:0] initx, inity, initr, initi;
05c0805b
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225 wire [7:0] initci, initb;
226 wire initxs, initys, initrs, initis;
227
534b3903
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228 // Values after the number of iterations denoted by the subscript.
229 reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
230 reg [7:0] stageci [2:1], stageb [2:1];
231 reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b 232
534b3903 233 reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b 234
534b3903
JW
235 assign initx = state[0] ? rx :
236 state[1] ? stagex[1] :
237 stagex[2];
238 assign inity = state[0] ? ry :
239 state[1] ? stagey[1] :
240 stagey[2];
241 assign initr = state[0] ? rx :
242 state[1] ? stager[1] :
243 stager[2];
244 assign initi = state[0] ? ry :
245 state[1] ? stagei[1] :
246 stagei[2];
247 assign initxs = state[0] ? rxsign :
248 state[1] ? stagexs[1] :
249 stagexs[2];
250 assign initys = state[0] ? rysign :
251 state[1] ? stageys[1] :
252 stageys[2];
253 assign initrs = state[0] ? rxsign :
254 state[1] ? stagers[1] :
255 stagers[2];
256 assign initis = state[0] ? rysign :
257 state[1] ? stageis[1] :
258 stageis[2];
259 assign initb = state[0] ? 8'b11111111 :
260 state[1] ? stageb[1] :
261 stageb[2];
262 assign initci = state[0] ? 8'b00000000 :
3068fa61
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263 state[1] ? stageci[1] :
264 stageci[2];
05c0805b
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265
266 reg [7:0] out;
251788d8
JW
267
268 // We detect when the state should be poked by a high negedge followed
fb8d158b
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269 // by a high posedge -- if that happens, then we're guaranteed that the
270 // state following the current state will be 3'b100.
251788d8 271 reg lastneg;
265061f2 272 always @(negedge mclk)
251788d8 273 lastneg <= pixclk;
05c0805b
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274
275 always @(posedge mclk)
276 begin
251788d8
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277 if (lastneg && pixclk) // If a pixclk has happened, the state should be reset.
278 state <= 3'b100;
279 else // Otherwise, just poke it forward.
280 state <= {state[1], state[0], state[2]};
281
534b3903
JW
282 // Data output handling
283 if (state[0]) begin
05c0805b 284 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b 285 end
3068fa61 286 if (state[1]) begin
534b3903
JW
287 out <= ~mb[`MAXOUTN] + colorofs;
288 end
289
3068fa61 290 if (state[0]) begin // PnR0 in, PnR2 out
534b3903
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291 stagex[2] <= xprop[`MAXOUTN];
292 stagey[2] <= yprop[`MAXOUTN];
293 stager[2] <= mr[`MAXOUTN];
294 stagei[2] <= mi[`MAXOUTN];
295 stagexs[2] <= xsprop[`MAXOUTN];
296 stageys[2] <= ysprop[`MAXOUTN];
297 stagers[2] <= mrs[`MAXOUTN];
298 stageis[2] <= mis[`MAXOUTN];
299 stageb[2] <= mb[`MAXOUTN];
300 stageci[2] <= curiter[`MAXOUTN];
301 end
302
3068fa61 303 if (state[2]) begin // PnR2 in, PnR1 out
534b3903
JW
304 stagex[1] <= xprop[`MAXOUTN];
305 stagey[1] <= yprop[`MAXOUTN];
306 stager[1] <= mr[`MAXOUTN];
307 stagei[1] <= mi[`MAXOUTN];
308 stagexs[1] <= xsprop[`MAXOUTN];
309 stageys[1] <= ysprop[`MAXOUTN];
310 stagers[1] <= mrs[`MAXOUTN];
311 stageis[1] <= mis[`MAXOUTN];
312 stageb[1] <= mb[`MAXOUTN];
313 stageci[1] <= curiter[`MAXOUTN];
314 end
05c0805b
JW
315 end
316
317 MandelUnit mu0(
318 mclk,
319 initx, inity, initxs, initys,
320 initr, initi, initrs, initis,
321 initb, initci,
322 xprop[0], yprop[0], xsprop[0], ysprop[0],
323 mr[0], mi[0], mrs[0], mis[0],
324 mb[0], curiter[0]);
325
326 MandelUnit mu1(mclk,
327 xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
328 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
329 MandelUnit mu2(mclk,
330 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
331 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
332 MandelUnit mu3(mclk,
333 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
334 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
335 MandelUnit mu4(mclk,
336 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
337 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
338 MandelUnit mu5(mclk,
339 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
340 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
341 MandelUnit mu6(mclk,
342 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
343 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
344 MandelUnit mu7(mclk,
345 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
346 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
347 MandelUnit mu8(mclk,
348 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
349 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
350 MandelUnit mu9(mclk,
351 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
352 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
281eac32
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353 MandelUnit mua(mclk,
354 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
355 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
356 MandelUnit mub(mclk,
357 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
358 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
281eac32 359
05c0805b
JW
360endmodule
361
362module Logo(
363 input pixclk,
364 input [11:0] x, y,
365 output wire enb,
366 output wire [2:0] red, green, output wire [1:0] blue);
367
368 reg [1:0] logo[8191:0];
369 initial $readmemb("logo.readmemb", logo);
370
371 assign enb = (x < 96) && (y < 64);
372 wire [12:0] addr = {y[5:0], x[6:0]};
373 wire [1:0] data = logo[addr];
374 assign {red, green, blue} =
375 (data == 2'b00) ? 8'b00000000 :
376 ((data == 2'b01) ? 8'b00011100 :
377 ((data == 2'b10) ? 8'b11100000 :
378 8'b11111111));
379endmodule
380
381module MandelTop(
382 input gclk, output wire dcmok,
383 output wire vs, hs,
384 output wire [2:0] red, green, output [1:0] blue,
385 input left, right, up, down, rst, cycle, logooff,
386 input [2:0] scale);
387
534b3903
JW
388
389 wire pixclk, mclk, gclk2, clk;
390 wire dcm1ok, dcm2ok;
c3ed4329 391 assign dcmok = dcm1ok && dcm2ok;
265061f2 392
c3ed4329 393 IBUFG typeA(.O(clk), .I(gclk));
534b3903 394
c3ed4329
JW
395 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
396 .CLKIN_IN(clk),
397 .CLKFX_OUT(pixclk),
398 .LOCKED_OUT(dcm1ok)
399 );
534b3903 400
c3ed4329
JW
401 mandelDCM dcm2(
402 .CLKIN_IN(clk),
403 .CLKFX_OUT(mclk),
404 .LOCKED_OUT(dcm2ok)
405 );
534b3903 406
05c0805b 407 wire border;
05c0805b 408 wire [11:0] x, y;
92e851e1 409 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b
JW
410 reg [5:0] slowctr = 0;
411 reg [7:0] colorcycle = 0;
412 wire [11:0] realx, realy;
413
414 wire logoenb;
415 wire [2:0] mandelr, mandelg, logor, logog;
416 wire [1:0] mandelb, logob;
417
534b3903 418
05c0805b
JW
419
420 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903 421 Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b
JW
422 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
423
424 assign {red,green,blue} =
425 border ? 8'b00000000 :
426 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
427
428 always @(posedge vs)
429 begin
430 if (rst)
431 begin
432 xofs <= -`XRES/2;
433 yofs <= -`YRES/2;
434 colorcycle <= 0;
435 end else begin
436 if (up) yofs <= yofs + 1;
437 else if (down) yofs <= yofs - 1;
438
439 if (left) xofs <= xofs + 1;
440 else if (right) xofs <= xofs - 1;
441
442 if (slowctr == 0)
443 colorcycle <= colorcycle + 1;
444 end
445
446 if (slowctr == 12)
447 slowctr <= 0;
448 else
449 slowctr <= slowctr + 1;
450 end
451endmodule
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