what the fuck, this was supposed to get the slice count down, instead it's up to...
[mandelfpga.git] / Main.v
CommitLineData
cf1ae842 1/*
05c0805b
JW
2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
JW
12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
fb8d158b 67 output reg ovf);
05c0805b
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68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x >> 1) : 0) +
fb8d158b
JW
74 (y[10] ? (x >> 2) : 0)) +
75 (((y[9] ? (x >> 3) : 0) +
76 (y[8] ? (x >> 4) : 0))+
77 ((y[7] ? (x >> 5) : 0) +
78 (y[6] ? (x >> 6) : 0))))+
79
05c0805b 80 (((y[5] ? (x >> 7) : 0) +
fb8d158b 81 (y[4] ? (x >> 8) : 0)+
05c0805b 82 (y[3] ? (x >> 9) : 0)) +
fb8d158b 83 ((y[2] ? (x >> 10): 0) +
05c0805b
JW
84 (y[1] ? (x >> 11): 0) +
85 (y[0] ? (x >> 12): 0)));
86 sign <= xsign ^ ysign;
87 end
88
89endmodule
90
91module Multiplier(
92 input clk,
92e851e1 93 input [12:0] x, y,
05c0805b 94 input xsign, ysign,
92e851e1 95 output wire [12:0] out,
05c0805b 96 output wire sign,
fb8d158b 97 output wire overflow);
05c0805b
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98
99 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
100
101endmodule
102
fb8d158b 103// Yuq.
05c0805b
JW
104module MandelUnit(
105 input clk,
106 input [12:0] x, y,
107 input xsign, ysign,
92e851e1 108 input [14:0] r, i,
05c0805b
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109 input rsign, isign,
110 input [7:0] ibail, icuriter,
111 output reg [12:0] xout, yout,
112 output reg xsout, ysout,
92e851e1 113 output reg [14:0] rout, iout,
05c0805b
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114 output reg rsout, isout,
115 output reg [7:0] obail, ocuriter);
116
6cdf39e2
JW
117 wire [13:0] r2, i2;
118 wire [14:0] ri, diff;
9032b2b5 119 wire [15:0] twocdiff;
05c0805b 120 wire r2sign, i2sign, risign, dsign;
6cdf39e2
JW
121 wire [13:0] bigsum;
122 wire bigsum_ovf;
05c0805b
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123
124 reg [12:0] xd, yd;
2afeab21 125 reg ineedbaild;
05c0805b
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126 reg xsd, ysd;
127 reg [7:0] ibaild, curiterd;
128
129 assign ri[0] = 0;
130
a3a4354b
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131 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
132 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
133 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
05c0805b 134
6cdf39e2
JW
135 assign bigsum = r2[12:0] + i2[12:0];
136 assign bigsum_ovf = bigsum[13] | r2[13] | i2[13];
2afeab21 137
9032b2b5
JW
138 assign twocdiff = r2 - i2;
139 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
140 assign dsign = twocdiff[15];
2afeab21
JW
141
142 wire [15:0] twocrout = xd - diff;
143 wire [15:0] twociout = yd - ri;
05c0805b
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144
145 always @ (posedge clk)
146 begin
147 xd <= x;
148 yd <= y;
149 xsd <= xsign;
150 ysd <= ysign;
151 xout <= xd;
152 yout <= yd;
153 xsout <= xsd;
154 ysout <= ysd;
155 ibaild <= ibail;
156 curiterd <= icuriter;
2afeab21 157 ineedbaild <= r[13] | r[14] | i[13] | i[14];
05c0805b 158
2afeab21 159 // r^2 - i^2 + x
05c0805b 160 if (xsd ^ dsign) begin
2afeab21
JW
161 if (twocrout[15]) begin // diff > xd
162 rout <= -twocrout;
05c0805b
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163 rsout <= dsign;
164 end else begin
2afeab21 165 rout <= twocrout;
05c0805b
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166 rsout <= xsd;
167 end
168 end else begin
169 rout <= diff + xd;
2afeab21 170 rsout <= xsd; // xsd == dsign
05c0805b
JW
171 end
172
2afeab21 173 // 2 * r * i + y
05c0805b 174 if (ysd ^ risign) begin
2afeab21
JW
175 if (twociout[15]) begin // ri > yd
176 iout <= -twociout;
05c0805b
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177 isout <= risign;
178 end else begin
2afeab21 179 iout <= twociout;
05c0805b
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180 isout <= ysd;
181 end
182 end else begin
183 iout <= ri + yd;
184 isout <= ysd;
185 end
186
187 // If we haven't bailed out, and we meet any of the bailout conditions,
188 // bail out now. Otherwise, leave the bailout at whatever it was before.
2afeab21 189 if ((ibaild == 255) && (bigsum_ovf | ineedbaild))
05c0805b
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190 obail <= curiterd;
191 else
192 obail <= ibaild;
193 ocuriter <= curiterd + 8'b1;
194 end
195
196endmodule
197
198module Mandelbrot(
199 input mclk,
200 input pixclk,
201 input [11:0] x, y,
92e851e1 202 input [13:0] xofs, yofs,
05c0805b
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203 input [7:0] colorofs,
204 input [2:0] scale,
205 output reg [2:0] red, green, output reg [1:0] blue);
281eac32 206
534b3903 207`define MAXOUTN 11
05c0805b
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208
209 wire [12:0] rx, ry;
210 wire [13:0] nx, ny;
211 wire rxsign, rysign;
212
213 assign nx = x + xofs;
214 assign ny = y + yofs;
215 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
216 assign rxsign = nx[13];
217 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
218 assign rysign = ny[13];
05c0805b 219
281eac32
JW
220 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
221 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
222 wire [7:0] mb[`MAXOUTN:0];
223 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
224 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
225 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 226
79af494a
JW
227 reg [14:0] initx, inity, initr, initi;
228 reg [7:0] initci, initb;
229 reg initxs, initys, initrs, initis;
05c0805b 230
534b3903
JW
231 // Values after the number of iterations denoted by the subscript.
232 reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
233 reg [7:0] stageci [2:1], stageb [2:1];
234 reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b 235
534b3903 236 reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b 237
79af494a
JW
238 // States are advanced one from what they should be, so that they'll
239 // get there on the _next_ mclk.
240 always @(posedge mclk)
241 begin
242 initx <= (state[2]) ? rx :
243 (state[0]) ? stagex[1] :
244 (state[1]) ? stagex[2] : 0;
245 inity <= (state[2]) ? ry :
246 (state[0]) ? stagey[1] :
247 (state[1]) ? stagey[2] : 0;
248 initr <= (state[2]) ? rx :
249 (state[0]) ? stager[1] :
250 (state[1]) ? stager[2] : 0;
251 initi <= (state[2]) ? ry :
252 (state[0]) ? stagei[1] :
253 (state[1]) ? stagei[2] : 0;
254 initxs <= (state[2]) ? rxsign :
255 (state[0]) ? stagexs[1] :
256 (state[1]) ? stagexs[2] : 0;
257 initys <= (state[2]) ? rysign :
258 (state[0]) ? stageys[1] :
259 (state[1]) ? stageys[2] : 0;
260 initrs <= (state[2]) ? rxsign :
261 (state[0]) ? stagers[1] :
262 (state[1]) ? stagers[2] : 0;
263 initis <= (state[2]) ? rysign :
264 (state[0]) ? stageis[1] :
265 (state[1]) ? stageis[2] : 0;
266 initb <= (state[2]) ? 8'b11111111 :
267 (state[0]) ? stageb[1] :
268 (state[1]) ? stageb[2] : 0;
269 initci <= (state[2]) ? 8'b00000000 :
270 (state[0]) ? stageci[1] :
271 (state[1]) ? stageci[2] : 0;
272 end
05c0805b
JW
273
274 reg [7:0] out;
251788d8
JW
275
276 // We detect when the state should be poked by a high negedge followed
fb8d158b
JW
277 // by a high posedge -- if that happens, then we're guaranteed that the
278 // state following the current state will be 3'b100.
251788d8 279 reg lastneg;
265061f2 280 always @(negedge mclk)
251788d8 281 lastneg <= pixclk;
05c0805b
JW
282
283 always @(posedge mclk)
284 begin
251788d8
JW
285 if (lastneg && pixclk) // If a pixclk has happened, the state should be reset.
286 state <= 3'b100;
287 else // Otherwise, just poke it forward.
a3a4354b
JW
288 case(state)
289 3'b001: state <= 3'b010;
290 3'b010: state <= 3'b100;
291 3'b100: state <= 3'b001;
292 endcase
251788d8 293
534b3903
JW
294 // Data output handling
295 if (state[0]) begin
05c0805b 296 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b 297 end
3068fa61 298 if (state[1]) begin
534b3903
JW
299 out <= ~mb[`MAXOUTN] + colorofs;
300 end
301
3068fa61 302 if (state[0]) begin // PnR0 in, PnR2 out
534b3903
JW
303 stagex[2] <= xprop[`MAXOUTN];
304 stagey[2] <= yprop[`MAXOUTN];
305 stager[2] <= mr[`MAXOUTN];
306 stagei[2] <= mi[`MAXOUTN];
307 stagexs[2] <= xsprop[`MAXOUTN];
308 stageys[2] <= ysprop[`MAXOUTN];
309 stagers[2] <= mrs[`MAXOUTN];
310 stageis[2] <= mis[`MAXOUTN];
311 stageb[2] <= mb[`MAXOUTN];
312 stageci[2] <= curiter[`MAXOUTN];
313 end
314
3068fa61 315 if (state[2]) begin // PnR2 in, PnR1 out
534b3903
JW
316 stagex[1] <= xprop[`MAXOUTN];
317 stagey[1] <= yprop[`MAXOUTN];
318 stager[1] <= mr[`MAXOUTN];
319 stagei[1] <= mi[`MAXOUTN];
320 stagexs[1] <= xsprop[`MAXOUTN];
321 stageys[1] <= ysprop[`MAXOUTN];
322 stagers[1] <= mrs[`MAXOUTN];
323 stageis[1] <= mis[`MAXOUTN];
324 stageb[1] <= mb[`MAXOUTN];
325 stageci[1] <= curiter[`MAXOUTN];
326 end
05c0805b
JW
327 end
328
329 MandelUnit mu0(
330 mclk,
331 initx, inity, initxs, initys,
332 initr, initi, initrs, initis,
333 initb, initci,
334 xprop[0], yprop[0], xsprop[0], ysprop[0],
335 mr[0], mi[0], mrs[0], mis[0],
336 mb[0], curiter[0]);
337
338 MandelUnit mu1(mclk,
339 xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
340 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
341 MandelUnit mu2(mclk,
342 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
343 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
344 MandelUnit mu3(mclk,
345 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
346 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
347 MandelUnit mu4(mclk,
348 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
349 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
350 MandelUnit mu5(mclk,
351 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
352 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
353 MandelUnit mu6(mclk,
354 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
355 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
356 MandelUnit mu7(mclk,
357 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
358 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
359 MandelUnit mu8(mclk,
360 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
361 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
362 MandelUnit mu9(mclk,
363 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
364 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
281eac32
JW
365 MandelUnit mua(mclk,
366 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
367 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
368 MandelUnit mub(mclk,
369 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
370 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
281eac32 371
05c0805b
JW
372endmodule
373
374module Logo(
375 input pixclk,
376 input [11:0] x, y,
377 output wire enb,
378 output wire [2:0] red, green, output wire [1:0] blue);
379
380 reg [1:0] logo[8191:0];
381 initial $readmemb("logo.readmemb", logo);
382
383 assign enb = (x < 96) && (y < 64);
384 wire [12:0] addr = {y[5:0], x[6:0]};
385 wire [1:0] data = logo[addr];
386 assign {red, green, blue} =
387 (data == 2'b00) ? 8'b00000000 :
388 ((data == 2'b01) ? 8'b00011100 :
389 ((data == 2'b10) ? 8'b11100000 :
390 8'b11111111));
391endmodule
392
393module MandelTop(
394 input gclk, output wire dcmok,
395 output wire vs, hs,
396 output wire [2:0] red, green, output [1:0] blue,
397 input left, right, up, down, rst, cycle, logooff,
398 input [2:0] scale);
399
534b3903
JW
400
401 wire pixclk, mclk, gclk2, clk;
402 wire dcm1ok, dcm2ok;
c3ed4329 403 assign dcmok = dcm1ok && dcm2ok;
265061f2 404
c3ed4329 405 IBUFG typeA(.O(clk), .I(gclk));
534b3903 406
c3ed4329
JW
407 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
408 .CLKIN_IN(clk),
409 .CLKFX_OUT(pixclk),
410 .LOCKED_OUT(dcm1ok)
411 );
534b3903 412
c3ed4329
JW
413 mandelDCM dcm2(
414 .CLKIN_IN(clk),
415 .CLKFX_OUT(mclk),
416 .LOCKED_OUT(dcm2ok)
417 );
534b3903 418
05c0805b 419 wire border;
05c0805b 420 wire [11:0] x, y;
92e851e1 421 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b
JW
422 reg [5:0] slowctr = 0;
423 reg [7:0] colorcycle = 0;
424 wire [11:0] realx, realy;
425
426 wire logoenb;
427 wire [2:0] mandelr, mandelg, logor, logog;
428 wire [1:0] mandelb, logob;
429
05c0805b 430 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903 431 Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b
JW
432 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
433
434 assign {red,green,blue} =
435 border ? 8'b00000000 :
436 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
437
438 always @(posedge vs)
439 begin
440 if (rst)
441 begin
442 xofs <= -`XRES/2;
443 yofs <= -`YRES/2;
444 colorcycle <= 0;
445 end else begin
446 if (up) yofs <= yofs + 1;
447 else if (down) yofs <= yofs - 1;
448
449 if (left) xofs <= xofs + 1;
450 else if (right) xofs <= xofs - 1;
451
452 if (slowctr == 0)
453 colorcycle <= colorcycle + 1;
454 end
455
456 if (slowctr == 12)
457 slowctr <= 0;
458 else
459 slowctr <= slowctr + 1;
460 end
461endmodule
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