[mandelfpga.git] / Main.v

/* 
 * MandelFPGA
 * by Joshua Wise and Chris Lu
 * 
 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
 * in real time on an FPGA.
 */

`define XRES 640
`define YRES 480
`define WHIRRRRR 27

module SyncGen(
	input pixclk,
	output reg vs, hs,
	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	output wire [11:0] xoutreal, youtreal,
	output reg border);
	
	reg [11:0] x = 0, y = 0;	// Used for generating border and timing.
	assign xoutreal = x;
	assign youtreal = y;
	
	parameter XFPORCH = 16;
	parameter XSYNC = 96;
	parameter XBPORCH = 48;
	
	parameter YFPORCH = 10;
	parameter YSYNC = 2;
	parameter YBPORCH = 29;

	always @(posedge pixclk)
	begin
		if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				y <= 0;
			else
				y <= y + 1;
			x <= 0;
		end else
			x <= x + 1;
			
		if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				yout <= 0;
			else
				yout <= yout + 1;
			xout <= 0;
		end else
			xout <= xout + 1;
		hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
		vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
		border <= (x > `XRES) || (y > `YRES);
	end
endmodule

// bits: 1.12

module NaiveMultiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output reg [12:0] out,
	output reg sign,
	output reg [1:0] ovf);

	always @(posedge clk)
	begin
		{ovf,out} <=
			(((y[12] ? (x     ) : 0)  +
			  (y[11] ? (x >> 1) : 0)  +
			  (y[10] ? (x >> 2) : 0)  +
			  (y[9]  ? (x >> 3) : 0)) +
			 ((y[8]  ? (x >> 4) : 0)  +
			  (y[7]  ? (x >> 5) : 0)  +
			  (y[6]  ? (x >> 6) : 0)))+
			(((y[5]  ? (x >> 7) : 0)  +
			  (y[4]  ? (x >> 8) : 0)  +
			  (y[3]  ? (x >> 9) : 0)) +
			 ((y[2]  ? (x >> 10): 0)  +
			  (y[1]  ? (x >> 11): 0)  +
			  (y[0]  ? (x >> 12): 0)));
		sign <= xsign ^ ysign;
	end

endmodule

module Multiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output wire [12:0] out,
	output wire sign,
	output wire [1:0] overflow);

	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);

endmodule

module MandelUnit(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	input [14:0] r, i,
	input rsign, isign,
	input [7:0] ibail, icuriter,
	output reg [12:0] xout, yout,
	output reg xsout, ysout,
	output reg [14:0] rout, iout,
	output reg rsout, isout,
	output reg [7:0] obail, ocuriter);

	wire [14:0] r2, i2, ri, diff;
	wire [15:0] twocdiff;
	wire r2sign, i2sign, risign, dsign;
	wire [16:0] bigsum;
	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;

	reg [12:0] xd, yd;
	reg rd, id;
	reg xsd, ysd;
	reg [7:0] ibaild, curiterd;

	assign ri[0] = 0;

	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});

	assign bigsum = r2 + i2;
	assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
	assign rin_ovf = rd;
	assign iin_ovf = id;
	assign twocdiff = r2 - i2;
	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
	assign dsign = twocdiff[15];

	always @ (posedge clk)
	begin
		xd <= x;
		yd <= y;
		xsd <= xsign;
		ysd <= ysign;
		xout <= xd;
		yout <= yd;
		xsout <= xsd;
		ysout <= ysd;
		ibaild <= ibail;
		curiterd <= icuriter;
		rd <= r[13] | r[14];
		id <= i[13] | i[14];

		if (xsd ^ dsign) begin
			if (diff > xd) begin
				rout <= diff - xd;
				rsout <= dsign;
			end else begin
				rout <= xd - diff;
				rsout <= xsd;
			end
		end else begin
			rout <= diff + xd;
			rsout <= xsd;
		end
		
		if (ysd ^ risign) begin
			if (ri > yd) begin
				iout <= ri - yd;
				isout <= risign;
			end else begin
				iout <= yd - ri;
				isout <= ysd;
			end
		end else begin
			iout <= ri + yd;
			isout <= ysd;
		end
		
		// If we haven't bailed out, and we meet any of the bailout conditions,
		// bail out now.  Otherwise, leave the bailout at whatever it was before.
		if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
			obail <= curiterd;
		else
			obail <= ibaild;
		ocuriter <= curiterd + 8'b1;
	end

endmodule

module Mandelbrot(
	input mclk,
	input pixclk,
	input [11:0] x, y,
	input [13:0] xofs, yofs,
	input [7:0] colorofs,
	input [2:0] scale,
	output reg [2:0] red, green, output reg [1:0] blue);

`define MAXOUTN 11
	
	wire [12:0] rx, ry;
	wire [13:0] nx, ny;
	wire rxsign, rysign;
	
	assign nx = x + xofs;
	assign ny = y + yofs;
	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	assign rxsign = nx[13];
	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	assign rysign = ny[13];
	

	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
	wire [7:0] mb[`MAXOUTN:0];
	wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
	wire [7:0] curiter[`MAXOUTN:0];
	
	wire [14:0] initx, inity, initr, initi;
	wire [7:0] initci, initb;
	wire initxs, initys, initrs, initis;
	
	// Values after the number of iterations denoted by the subscript.
	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
	reg [7:0] stageci [2:1], stageb [2:1];
	reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
	
	reg [2:0] state = 3'b001;	// One-hot encoded state.
	
	assign initx = state[0] ? rx :
	               state[1] ? stagex[1] :
	               stagex[2];
	assign inity = state[0] ? ry :
	               state[1] ? stagey[1] :
	               stagey[2];
	assign initr = state[0] ? rx :
	               state[1] ? stager[1] :
	               stager[2];
	assign initi = state[0] ? ry :
	               state[1] ? stagei[1] :
	               stagei[2];
	assign initxs = state[0] ? rxsign :
	                state[1] ? stagexs[1] :
	                stagexs[2];
	assign initys = state[0] ? rysign :
	                state[1] ? stageys[1] :
	                stageys[2];
	assign initrs = state[0] ? rxsign :
	                state[1] ? stagers[1] :
	                stagers[2];
	assign initis = state[0] ? rysign :
	                state[1] ? stageis[1] :
	                stageis[2];
	assign initb = state[0] ? 8'b11111111 :
	               state[1] ? stageb[1] :
	               stageb[2];
	assign initci = state[0] ? 8'b00000000 :
	                state[1] ? stageci[1] : 
	                stageci[2];
	
	reg [7:0] out;
	reg typethea = 0;	// Whether we have typed the A.
	reg statekick = 0;	// State needs to be kicked back to 3'b010 on the next mclk.

	// This is guaranteed to converge after two pixclks.
	always @(negedge mclk)
		if (pixclk && !statekick) begin
			statekick <= 1;
		end else if (statekick) begin // This is the edge of the falling anus.
			statekick <= 0;
		end
	
	always @(posedge mclk)
	begin
		// Data output handling
		if (state[0]) begin
			{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
		end
		if (state[1]) begin
			out <= ~mb[`MAXOUTN] + colorofs;
		end
		
		if (state[0]) begin		// PnR0 in, PnR2 out
			stagex[2] <= xprop[`MAXOUTN];
			stagey[2] <= yprop[`MAXOUTN];
			stager[2] <= mr[`MAXOUTN];
			stagei[2] <= mi[`MAXOUTN];
			stagexs[2] <= xsprop[`MAXOUTN];
			stageys[2] <= ysprop[`MAXOUTN];
			stagers[2] <= mrs[`MAXOUTN];
			stageis[2] <= mis[`MAXOUTN];
			stageb[2] <= mb[`MAXOUTN];
			stageci[2] <= curiter[`MAXOUTN];
		end
		
		if (state[2]) begin	// PnR2 in, PnR1 out
			stagex[1] <= xprop[`MAXOUTN];
			stagey[1] <= yprop[`MAXOUTN];
			stager[1] <= mr[`MAXOUTN];
			stagei[1] <= mi[`MAXOUTN];
			stagexs[1] <= xsprop[`MAXOUTN];
			stageys[1] <= ysprop[`MAXOUTN];
			stagers[1] <= mrs[`MAXOUTN];
			stageis[1] <= mis[`MAXOUTN];
			stageb[1] <= mb[`MAXOUTN];
			stageci[1] <= curiter[`MAXOUTN];
		end
		
		if (statekick)		// If a pixclk has happened, the state should be reset.
			state <= 3'b010;
		else						// Otherwise, just poke it forward.
			state <= {state[1], state[0], state[2]};
	end

	MandelUnit mu0(
		mclk,
		initx, inity, initxs, initys,
		initr, initi, initrs, initis,
		initb, initci,
		xprop[0], yprop[0], xsprop[0], ysprop[0],
		mr[0], mi[0], mrs[0], mis[0],
		mb[0], curiter[0]);

	MandelUnit mu1(mclk,
		xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
		xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
	MandelUnit mu2(mclk,
		xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
		xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
	MandelUnit mu3(mclk,
		xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
		xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
	MandelUnit mu4(mclk,
		xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
		xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
	MandelUnit mu5(mclk,
		xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
		xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
	MandelUnit mu6(mclk,
		xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
		xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
	MandelUnit mu7(mclk,
		xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
		xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
	MandelUnit mu8(mclk,
		xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
		xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
	MandelUnit mu9(mclk,
		xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
		xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
	MandelUnit mua(mclk,
		xprop[9],  yprop[9],  xsprop[9],  ysprop[9],  mr[9],  mi[9],  mrs[9],  mis[9],  mb[9], curiter[9],
		xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
	MandelUnit mub(mclk,
		xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
		xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);

endmodule

module Logo(
	input pixclk,
	input [11:0] x, y,
	output wire enb,
	output wire [2:0] red, green, output wire [1:0] blue);
	
	reg [1:0] logo[8191:0];
	initial $readmemb("logo.readmemb", logo);
	
	assign enb = (x < 96) && (y < 64);
	wire [12:0] addr = {y[5:0], x[6:0]};
	wire [1:0] data = logo[addr];
	assign {red, green, blue} = 
		 (data == 2'b00) ? 8'b00000000 :
		((data == 2'b01) ? 8'b00011100 :
		((data == 2'b10) ? 8'b11100000 :
		                    8'b11111111));
endmodule

module MandelTop(
	input gclk, output wire dcmok,
	output wire vs, hs,
	output wire [2:0] red, green, output [1:0] blue,
	input left, right, up, down, rst, cycle, logooff,
	input [2:0] scale);


	wire pixclk, mclk, gclk2, clk;
	wire dcm1ok, dcm2ok;
	//assign dcmok = dcm1ok && dcm2ok;
	
	//IBUFG typeA(.O(clk), .I(gclk));
	
	//pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
	//	.CLKIN_IN(clk), 
	//	.CLKFX_OUT(pixclk),
	//	.LOCKED_OUT(dcm1ok)
	//	);
	
	//mandelDCM dcm2(
	//	.CLKIN_IN(clk),
	//	.CLKFX_OUT(mclk),
	//	.LOCKED_OUT(dcm2ok)
	//	);
	
	mainDCM dcm (
    .U1_CLKIN_IN(gclk), 
    .U1_CLKDV_OUT(pixclk), 
    .U2_CLKFX_OUT(mclk), 
    .U2_LOCKED_OUT(dcmok)
    );
	
	wire border;
	wire [11:0] x, y;
	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
	reg [5:0] slowctr = 0;
	reg [7:0] colorcycle = 0;
	wire [11:0] realx, realy;
	
	wire logoenb;
	wire [2:0] mandelr, mandelg, logor, logog;
	wire [1:0] mandelb, logob;
	
	
	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
	Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	
	assign {red,green,blue} =
		border ? 8'b00000000 :
		(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	
	always @(posedge vs)
	begin
		if (rst)
		begin
			xofs <= -`XRES/2;
			yofs <= -`YRES/2;
			colorcycle <= 0;
		end else begin
			if (up) yofs <= yofs + 1;
			else if (down) yofs <= yofs - 1;
			
			if (left) xofs <= xofs + 1;
			else if (right) xofs <= xofs - 1;
			
			if (slowctr == 0)
				colorcycle <= colorcycle + 1;
		end
		
		if (slowctr == 12)
			slowctr <= 0;
		else
			slowctr <= slowctr + 1;
	end
endmodule
Commit	Line	Data
cf1ae842	1	/*
05c0805b JW	2	* MandelFPGA
	3	* by Joshua Wise and Chris Lu
	4	*
	5	* An implementation of a pipelined algorithm to calculate the Mandelbrot set
	6	* in real time on an FPGA.
	7	*/
	8
	9	`define XRES 640
	10	`define YRES 480
281eac32	11	`define WHIRRRRR 27
05c0805b JW	12
	13	module SyncGen(
	14	input pixclk,
	15	output reg vs, hs,
	16	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	17	output wire [11:0] xoutreal, youtreal,
	18	output reg border);
	19
	20	reg [11:0] x = 0, y = 0; // Used for generating border and timing.
	21	assign xoutreal = x;
	22	assign youtreal = y;
	23
	24	parameter XFPORCH = 16;
	25	parameter XSYNC = 96;
	26	parameter XBPORCH = 48;
	27
	28	parameter YFPORCH = 10;
	29	parameter YSYNC = 2;
	30	parameter YBPORCH = 29;
	31
	32	always @(posedge pixclk)
	33	begin
	34	if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	35	begin
	36	if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	37	y <= 0;
	38	else
	39	y <= y + 1;
	40	x <= 0;
	41	end else
	42	x <= x + 1;
	43
	44	if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	45	begin
	46	if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	47	yout <= 0;
	48	else
	49	yout <= yout + 1;
	50	xout <= 0;
	51	end else
	52	xout <= xout + 1;
	53	hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
	54	vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
	55	border <= (x > `XRES) \|\| (y > `YRES);
	56	end
	57	endmodule
	58
	59	// bits: 1.12
	60
	61	module NaiveMultiplier(
	62	input clk,
	63	input [12:0] x, y,
	64	input xsign, ysign,
	65	output reg [12:0] out,
	66	output reg sign,
	67	output reg [1:0] ovf);
	68
	69	always @(posedge clk)
	70	begin
	71	{ovf,out} <=
	72	(((y[12] ? (x ) : 0) +
	73	(y[11] ? (x >> 1) : 0) +
	74	(y[10] ? (x >> 2) : 0) +
	75	(y[9] ? (x >> 3) : 0)) +
76	((y[8] ? (x >> 4) : 0) +
77	(y[7] ? (x >> 5) : 0) +
78	(y[6] ? (x >> 6) : 0)))+
79	(((y[5] ? (x >> 7) : 0) +
80	(y[4] ? (x >> 8) : 0) +
81	(y[3] ? (x >> 9) : 0)) +
82	((y[2] ? (x >> 10): 0) +
83	(y[1] ? (x >> 11): 0) +
84	(y[0] ? (x >> 12): 0)));
85	sign <= xsign ^ ysign;
86	end
87
88	endmodule
89
90	module Multiplier(
91	input clk,
92e851e1	92	input [12:0] x, y,
05c0805b	93	input xsign, ysign,
92e851e1	94	output wire [12:0] out,
05c0805b JW	95	output wire sign,
	96	output wire [1:0] overflow);
	97
	98	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
	99
	100	endmodule
	101
	102	module MandelUnit(
	103	input clk,
	104	input [12:0] x, y,
	105	input xsign, ysign,
92e851e1	106	input [14:0] r, i,
05c0805b JW	107	input rsign, isign,
	108	input [7:0] ibail, icuriter,
	109	output reg [12:0] xout, yout,
	110	output reg xsout, ysout,
92e851e1	111	output reg [14:0] rout, iout,
05c0805b JW	112	output reg rsout, isout,
	113	output reg [7:0] obail, ocuriter);
	114
92e851e1	115	wire [14:0] r2, i2, ri, diff;
9032b2b5	116	wire [15:0] twocdiff;
05c0805b JW	117	wire r2sign, i2sign, risign, dsign;
	118	wire [16:0] bigsum;
	119	wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
	120
	121	reg [12:0] xd, yd;
	122	reg rd, id;
	123	reg xsd, ysd;
	124	reg [7:0] ibaild, curiterd;
	125
	126	assign ri[0] = 0;
	127
92e851e1 JW	128	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
	129	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
	130	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
05c0805b JW	131
	132	assign bigsum = r2 + i2;
	133	assign bigsum_ovf = bigsum[16] \| bigsum[15] \| bigsum[14];
	134	assign rin_ovf = rd;
	135	assign iin_ovf = id;
9032b2b5 JW	136	assign twocdiff = r2 - i2;
	137	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
	138	assign dsign = twocdiff[15];
05c0805b JW	139
	140	always @ (posedge clk)
	141	begin
	142	xd <= x;
	143	yd <= y;
	144	xsd <= xsign;
	145	ysd <= ysign;
	146	xout <= xd;
	147	yout <= yd;
	148	xsout <= xsd;
	149	ysout <= ysd;
	150	ibaild <= ibail;
	151	curiterd <= icuriter;
92e851e1 JW	152	rd <= r[13] \| r[14];
92e851e1 JW	153	id <= i[13] \| i[14];
05c0805b JW	154
	155	if (xsd ^ dsign) begin
	156	if (diff > xd) begin
	157	rout <= diff - xd;
	158	rsout <= dsign;
	159	end else begin
	160	rout <= xd - diff;
	161	rsout <= xsd;
	162	end
	163	end else begin
	164	rout <= diff + xd;
	165	rsout <= xsd;
	166	end
	167
	168	if (ysd ^ risign) begin
	169	if (ri > yd) begin
	170	iout <= ri - yd;
	171	isout <= risign;
	172	end else begin
	173	iout <= yd - ri;
	174	isout <= ysd;
	175	end
	176	end else begin
	177	iout <= ri + yd;
	178	isout <= ysd;
	179	end
	180
	181	// If we haven't bailed out, and we meet any of the bailout conditions,
	182	// bail out now. Otherwise, leave the bailout at whatever it was before.
	183	if ((ibaild == 255) && (bigsum_ovf \| rin_ovf \| iin_ovf))
	184	obail <= curiterd;
	185	else
	186	obail <= ibaild;
	187	ocuriter <= curiterd + 8'b1;
	188	end
	189
	190	endmodule
	191
	192	module Mandelbrot(
	193	input mclk,
	194	input pixclk,
	195	input [11:0] x, y,
92e851e1	196	input [13:0] xofs, yofs,
05c0805b JW	197	input [7:0] colorofs,
	198	input [2:0] scale,
	199	output reg [2:0] red, green, output reg [1:0] blue);
281eac32	200
534b3903	201	`define MAXOUTN 11
05c0805b JW	202
	203	wire [12:0] rx, ry;
	204	wire [13:0] nx, ny;
	205	wire rxsign, rysign;
	206
	207	assign nx = x + xofs;
	208	assign ny = y + yofs;
	209	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	210	assign rxsign = nx[13];
	211	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	212	assign rysign = ny[13];
	213
	214
281eac32 JW	215	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
	216	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
	217	wire [7:0] mb[`MAXOUTN:0];
	218	wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
	219	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
	220	wire [7:0] curiter[`MAXOUTN:0];
05c0805b	221
f802110e	222	wire [14:0] initx, inity, initr, initi;
05c0805b JW	223	wire [7:0] initci, initb;
	224	wire initxs, initys, initrs, initis;
	225
534b3903 JW	226	// Values after the number of iterations denoted by the subscript.
	227	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
	228	reg [7:0] stageci [2:1], stageb [2:1];
	229	reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b	230
534b3903	231	reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b	232
534b3903 JW	233	assign initx = state[0] ? rx :
	234	state[1] ? stagex[1] :
	235	stagex[2];
	236	assign inity = state[0] ? ry :
	237	state[1] ? stagey[1] :
	238	stagey[2];
	239	assign initr = state[0] ? rx :
	240	state[1] ? stager[1] :
	241	stager[2];
	242	assign initi = state[0] ? ry :
	243	state[1] ? stagei[1] :
	244	stagei[2];
	245	assign initxs = state[0] ? rxsign :
	246	state[1] ? stagexs[1] :
	247	stagexs[2];
	248	assign initys = state[0] ? rysign :
	249	state[1] ? stageys[1] :
	250	stageys[2];
	251	assign initrs = state[0] ? rxsign :
	252	state[1] ? stagers[1] :
	253	stagers[2];
	254	assign initis = state[0] ? rysign :
	255	state[1] ? stageis[1] :
	256	stageis[2];
	257	assign initb = state[0] ? 8'b11111111 :
	258	state[1] ? stageb[1] :
	259	stageb[2];
	260	assign initci = state[0] ? 8'b00000000 :
3068fa61 JW	261	state[1] ? stageci[1] :
3068fa61 JW	262	stageci[2];
05c0805b JW	263
05c0805b JW	264	reg [7:0] out;
534b3903 JW	265	reg typethea = 0; // Whether we have typed the A.
	266	reg statekick = 0; // State needs to be kicked back to 3'b010 on the next mclk.
	267
	268	// This is guaranteed to converge after two pixclks.
265061f2 JW	269	always @(negedge mclk)
	270	if (pixclk && !statekick) begin
	271	statekick <= 1;
	272	end else if (statekick) begin // This is the edge of the falling anus.
	273	statekick <= 0;
	274	end
05c0805b JW	275
	276	always @(posedge mclk)
	277	begin
534b3903 JW	278	// Data output handling
534b3903 JW	279	if (state[0]) begin
05c0805b	280	{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b	281	end
3068fa61	282	if (state[1]) begin
534b3903 JW	283	out <= ~mb[`MAXOUTN] + colorofs;
	284	end
	285
3068fa61	286	if (state[0]) begin // PnR0 in, PnR2 out
534b3903 JW	287	stagex[2] <= xprop[`MAXOUTN];
	288	stagey[2] <= yprop[`MAXOUTN];
	289	stager[2] <= mr[`MAXOUTN];
	290	stagei[2] <= mi[`MAXOUTN];
	291	stagexs[2] <= xsprop[`MAXOUTN];
	292	stageys[2] <= ysprop[`MAXOUTN];
	293	stagers[2] <= mrs[`MAXOUTN];
	294	stageis[2] <= mis[`MAXOUTN];
	295	stageb[2] <= mb[`MAXOUTN];
	296	stageci[2] <= curiter[`MAXOUTN];
	297	end
	298
3068fa61	299	if (state[2]) begin // PnR2 in, PnR1 out
534b3903 JW	300	stagex[1] <= xprop[`MAXOUTN];
	301	stagey[1] <= yprop[`MAXOUTN];
	302	stager[1] <= mr[`MAXOUTN];
	303	stagei[1] <= mi[`MAXOUTN];
	304	stagexs[1] <= xsprop[`MAXOUTN];
	305	stageys[1] <= ysprop[`MAXOUTN];
	306	stagers[1] <= mrs[`MAXOUTN];
	307	stageis[1] <= mis[`MAXOUTN];
	308	stageb[1] <= mb[`MAXOUTN];
	309	stageci[1] <= curiter[`MAXOUTN];
	310	end
	311
	312	if (statekick) // If a pixclk has happened, the state should be reset.
	313	state <= 3'b010;
	314	else // Otherwise, just poke it forward.
	315	state <= {state[1], state[0], state[2]};
05c0805b JW	316	end
	317
	318	MandelUnit mu0(
	319	mclk,
	320	initx, inity, initxs, initys,
	321	initr, initi, initrs, initis,
	322	initb, initci,
	323	xprop[0], yprop[0], xsprop[0], ysprop[0],
	324	mr[0], mi[0], mrs[0], mis[0],
	325	mb[0], curiter[0]);
	326
	327	MandelUnit mu1(mclk,
	328	xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
	329	xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
	330	MandelUnit mu2(mclk,
	331	xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
	332	xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
	333	MandelUnit mu3(mclk,
	334	xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
	335	xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
	336	MandelUnit mu4(mclk,
	337	xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
	338	xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
	339	MandelUnit mu5(mclk,
	340	xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
	341	xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
	342	MandelUnit mu6(mclk,
	343	xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
	344	xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
	345	MandelUnit mu7(mclk,
	346	xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
	347	xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
	348	MandelUnit mu8(mclk,
	349	xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
	350	xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
	351	MandelUnit mu9(mclk,
	352	xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
	353	xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
281eac32 JW	354	MandelUnit mua(mclk,
	355	xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
	356	xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
	357	MandelUnit mub(mclk,
	358	xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
	359	xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
281eac32	360
05c0805b JW	361	endmodule
	362
	363	module Logo(
	364	input pixclk,
	365	input [11:0] x, y,
	366	output wire enb,
	367	output wire [2:0] red, green, output wire [1:0] blue);
	368
	369	reg [1:0] logo[8191:0];
	370	initial $readmemb("logo.readmemb", logo);
	371
	372	assign enb = (x < 96) && (y < 64);
	373	wire [12:0] addr = {y[5:0], x[6:0]};
	374	wire [1:0] data = logo[addr];
	375	assign {red, green, blue} =
	376	(data == 2'b00) ? 8'b00000000 :
	377	((data == 2'b01) ? 8'b00011100 :
	378	((data == 2'b10) ? 8'b11100000 :
	379	8'b11111111));
	380	endmodule
	381
	382	module MandelTop(
	383	input gclk, output wire dcmok,
	384	output wire vs, hs,
	385	output wire [2:0] red, green, output [1:0] blue,
	386	input left, right, up, down, rst, cycle, logooff,
	387	input [2:0] scale);
	388
534b3903 JW	389
	390	wire pixclk, mclk, gclk2, clk;
	391	wire dcm1ok, dcm2ok;
265061f2 JW	392	//assign dcmok = dcm1ok && dcm2ok;
	393
	394	//IBUFG typeA(.O(clk), .I(gclk));
534b3903	395
265061f2 JW	396	//pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
	397	// .CLKIN_IN(clk),
	398	// .CLKFX_OUT(pixclk),
	399	// .LOCKED_OUT(dcm1ok)
	400	// );
534b3903	401
265061f2 JW	402	//mandelDCM dcm2(
	403	// .CLKIN_IN(clk),
	404	// .CLKFX_OUT(mclk),
	405	// .LOCKED_OUT(dcm2ok)
	406	// );
534b3903	407
265061f2 JW	408	mainDCM dcm (
	409	.U1_CLKIN_IN(gclk),
	410	.U1_CLKDV_OUT(pixclk),
	411	.U2_CLKFX_OUT(mclk),
	412	.U2_LOCKED_OUT(dcmok)
	413	);
534b3903	414
05c0805b	415	wire border;
05c0805b	416	wire [11:0] x, y;
92e851e1	417	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b JW	418	reg [5:0] slowctr = 0;
	419	reg [7:0] colorcycle = 0;
	420	wire [11:0] realx, realy;
	421
	422	wire logoenb;
	423	wire [2:0] mandelr, mandelg, logor, logog;
	424	wire [1:0] mandelb, logob;
	425
534b3903	426
05c0805b JW	427
05c0805b JW	428	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903	429	Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b JW	430	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	431
	432	assign {red,green,blue} =
	433	border ? 8'b00000000 :
	434	(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	435
	436	always @(posedge vs)
	437	begin
	438	if (rst)
	439	begin
	440	xofs <= -`XRES/2;
	441	yofs <= -`YRES/2;
	442	colorcycle <= 0;
	443	end else begin
	444	if (up) yofs <= yofs + 1;
	445	else if (down) yofs <= yofs - 1;
	446
	447	if (left) xofs <= xofs + 1;
	448	else if (right) xofs <= xofs - 1;
	449
	450	if (slowctr == 0)
	451	colorcycle <= colorcycle + 1;
	452	end
	453
	454	if (slowctr == 12)
	455	slowctr <= 0;
	456	else
	457	slowctr <= slowctr + 1;
	458	end
	459	endmodule