Optimization baseline, 77.788MHz, 4894 Slices, 1849 slice FFs, 9078 LUTs
[mandelfpga.git] / Main.v
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cf1ae842 1/*
05c0805b
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2 * MandelFPGA
3 * by Joshua Wise and Chris Lu
4 *
5 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
6 * in real time on an FPGA.
7 */
8
9`define XRES 640
10`define YRES 480
281eac32 11`define WHIRRRRR 27
05c0805b
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12
13module SyncGen(
14 input pixclk,
15 output reg vs, hs,
16 output reg [11:0] xout = `WHIRRRRR, yout = 0,
17 output wire [11:0] xoutreal, youtreal,
18 output reg border);
19
20 reg [11:0] x = 0, y = 0; // Used for generating border and timing.
21 assign xoutreal = x;
22 assign youtreal = y;
23
24 parameter XFPORCH = 16;
25 parameter XSYNC = 96;
26 parameter XBPORCH = 48;
27
28 parameter YFPORCH = 10;
29 parameter YSYNC = 2;
30 parameter YBPORCH = 29;
31
32 always @(posedge pixclk)
33 begin
34 if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
35 begin
36 if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
37 y <= 0;
38 else
39 y <= y + 1;
40 x <= 0;
41 end else
42 x <= x + 1;
43
44 if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
45 begin
46 if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
47 yout <= 0;
48 else
49 yout <= yout + 1;
50 xout <= 0;
51 end else
52 xout <= xout + 1;
53 hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
54 vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
55 border <= (x > `XRES) || (y > `YRES);
56 end
57endmodule
58
59// bits: 1.12
60
61module NaiveMultiplier(
62 input clk,
63 input [12:0] x, y,
64 input xsign, ysign,
65 output reg [12:0] out,
66 output reg sign,
67 output reg [1:0] ovf);
68
69 always @(posedge clk)
70 begin
71 {ovf,out} <=
72 (((y[12] ? (x ) : 0) +
73 (y[11] ? (x >> 1) : 0) +
74 (y[10] ? (x >> 2) : 0) +
75 (y[9] ? (x >> 3) : 0)) +
76 ((y[8] ? (x >> 4) : 0) +
77 (y[7] ? (x >> 5) : 0) +
78 (y[6] ? (x >> 6) : 0)))+
79 (((y[5] ? (x >> 7) : 0) +
80 (y[4] ? (x >> 8) : 0) +
81 (y[3] ? (x >> 9) : 0)) +
82 ((y[2] ? (x >> 10): 0) +
83 (y[1] ? (x >> 11): 0) +
84 (y[0] ? (x >> 12): 0)));
85 sign <= xsign ^ ysign;
86 end
87
88endmodule
89
90module Multiplier(
91 input clk,
92e851e1 92 input [12:0] x, y,
05c0805b 93 input xsign, ysign,
92e851e1 94 output wire [12:0] out,
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95 output wire sign,
96 output wire [1:0] overflow);
97
98 NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
99
100endmodule
101
102module MandelUnit(
103 input clk,
104 input [12:0] x, y,
105 input xsign, ysign,
92e851e1 106 input [14:0] r, i,
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107 input rsign, isign,
108 input [7:0] ibail, icuriter,
109 output reg [12:0] xout, yout,
110 output reg xsout, ysout,
92e851e1 111 output reg [14:0] rout, iout,
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112 output reg rsout, isout,
113 output reg [7:0] obail, ocuriter);
114
92e851e1 115 wire [14:0] r2, i2, ri, diff;
9032b2b5 116 wire [15:0] twocdiff;
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117 wire r2sign, i2sign, risign, dsign;
118 wire [16:0] bigsum;
119 wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
120
121 reg [12:0] xd, yd;
122 reg rd, id;
123 reg xsd, ysd;
124 reg [7:0] ibaild, curiterd;
125
126 assign ri[0] = 0;
127
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128 Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
129 Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
130 Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
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131
132 assign bigsum = r2 + i2;
133 assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
134 assign rin_ovf = rd;
135 assign iin_ovf = id;
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136 assign twocdiff = r2 - i2;
137 assign diff = twocdiff[15] ? -twocdiff : twocdiff;
138 assign dsign = twocdiff[15];
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139
140 always @ (posedge clk)
141 begin
142 xd <= x;
143 yd <= y;
144 xsd <= xsign;
145 ysd <= ysign;
146 xout <= xd;
147 yout <= yd;
148 xsout <= xsd;
149 ysout <= ysd;
150 ibaild <= ibail;
151 curiterd <= icuriter;
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152 rd <= r[13] | r[14];
153 id <= i[13] | i[14];
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154
155 if (xsd ^ dsign) begin
156 if (diff > xd) begin
157 rout <= diff - xd;
158 rsout <= dsign;
159 end else begin
160 rout <= xd - diff;
161 rsout <= xsd;
162 end
163 end else begin
164 rout <= diff + xd;
165 rsout <= xsd;
166 end
167
168 if (ysd ^ risign) begin
169 if (ri > yd) begin
170 iout <= ri - yd;
171 isout <= risign;
172 end else begin
173 iout <= yd - ri;
174 isout <= ysd;
175 end
176 end else begin
177 iout <= ri + yd;
178 isout <= ysd;
179 end
180
181 // If we haven't bailed out, and we meet any of the bailout conditions,
182 // bail out now. Otherwise, leave the bailout at whatever it was before.
183 if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
184 obail <= curiterd;
185 else
186 obail <= ibaild;
187 ocuriter <= curiterd + 8'b1;
188 end
189
190endmodule
191
192module Mandelbrot(
193 input mclk,
194 input pixclk,
195 input [11:0] x, y,
92e851e1 196 input [13:0] xofs, yofs,
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197 input [7:0] colorofs,
198 input [2:0] scale,
199 output reg [2:0] red, green, output reg [1:0] blue);
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200
201`define MAXOUTN 12
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202
203 wire [12:0] rx, ry;
204 wire [13:0] nx, ny;
205 wire rxsign, rysign;
206
207 assign nx = x + xofs;
208 assign ny = y + yofs;
209 assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
210 assign rxsign = nx[13];
211 assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
212 assign rysign = ny[13];
213
214
281eac32
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215 wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
216 wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
217 wire [7:0] mb[`MAXOUTN:0];
218 wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
219 wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
220 wire [7:0] curiter[`MAXOUTN:0];
05c0805b 221
f802110e 222 wire [14:0] initx, inity, initr, initi;
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223 wire [7:0] initci, initb;
224 wire initxs, initys, initrs, initis;
225
92e851e1 226 reg [14:0] loopx, loopy, loopr, loopi;
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227 reg [7:0] loopci, loopb;
228 reg loopxs, loopys, looprs, loopis;
229
230 reg state = 0;
231
232 // On pixclk = 1,
233 // A new value to be loaded comes in, and a value in need of loopback comes out.
234 // On pixclk = 0,
235 // A new value in need of loopback comes in, and a completed value comes out.
236
237 assign initx = state ? rx : loopx;
238 assign inity = state ? ry : loopy;
239 assign initr = state ? rx : loopr;
240 assign initi = state ? ry : loopi;
241 assign initxs = state ? rxsign : loopxs;
242 assign initys = state ? rysign : loopys;
243 assign initrs = state ? rxsign : looprs;
244 assign initis = state ? rysign : loopis;
245 assign initb = state ? 8'b11111111 : loopb;
246 assign initci = state ? 8'b00000000 : loopci;
247
248 reg [7:0] out;
249 reg pixclksync;
250 always @(negedge mclk)
251 pixclksync <= ~pixclk;
252
253 always @(posedge mclk)
254 begin
255 if (!state) begin
281eac32 256 out <= ~mb[`MAXOUTN] + colorofs;
05c0805b
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257 end else begin
258 {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
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259 loopx <= xprop[`MAXOUTN];
260 loopy <= yprop[`MAXOUTN];
261 loopr <= mr[`MAXOUTN];
262 loopi <= mi[`MAXOUTN];
263 loopxs <= xsprop[`MAXOUTN];
264 loopys <= ysprop[`MAXOUTN];
265 looprs <= mrs[`MAXOUTN];
266 loopis <= mis[`MAXOUTN];
267 loopb <= mb[`MAXOUTN];
268 loopci <= curiter[`MAXOUTN];
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269 end
270 state <= ~pixclksync;
271 end
272
273 MandelUnit mu0(
274 mclk,
275 initx, inity, initxs, initys,
276 initr, initi, initrs, initis,
277 initb, initci,
278 xprop[0], yprop[0], xsprop[0], ysprop[0],
279 mr[0], mi[0], mrs[0], mis[0],
280 mb[0], curiter[0]);
281
282 MandelUnit mu1(mclk,
283 xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
284 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
285 MandelUnit mu2(mclk,
286 xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
287 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
288 MandelUnit mu3(mclk,
289 xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
290 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
291 MandelUnit mu4(mclk,
292 xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
293 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
294 MandelUnit mu5(mclk,
295 xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
296 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
297 MandelUnit mu6(mclk,
298 xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
299 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
300 MandelUnit mu7(mclk,
301 xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
302 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
303 MandelUnit mu8(mclk,
304 xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
305 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
306 MandelUnit mu9(mclk,
307 xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
308 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
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309 MandelUnit mua(mclk,
310 xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9],
311 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10]);
312 MandelUnit mub(mclk,
313 xprop[10], yprop[10], xsprop[10], ysprop[10], mr[10], mi[10], mrs[10], mis[10], mb[10], curiter[10],
314 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11]);
315 MandelUnit muc(mclk,
316 xprop[11], yprop[11], xsprop[11], ysprop[11], mr[11], mi[11], mrs[11], mis[11], mb[11], curiter[11],
317 xprop[12], yprop[12], xsprop[12], ysprop[12], mr[12], mi[12], mrs[12], mis[12], mb[12], curiter[12]);
318
05c0805b
JW
319endmodule
320
321module Logo(
322 input pixclk,
323 input [11:0] x, y,
324 output wire enb,
325 output wire [2:0] red, green, output wire [1:0] blue);
326
327 reg [1:0] logo[8191:0];
328 initial $readmemb("logo.readmemb", logo);
329
330 assign enb = (x < 96) && (y < 64);
331 wire [12:0] addr = {y[5:0], x[6:0]};
332 wire [1:0] data = logo[addr];
333 assign {red, green, blue} =
334 (data == 2'b00) ? 8'b00000000 :
335 ((data == 2'b01) ? 8'b00011100 :
336 ((data == 2'b10) ? 8'b11100000 :
337 8'b11111111));
338endmodule
339
340module MandelTop(
341 input gclk, output wire dcmok,
342 output wire vs, hs,
343 output wire [2:0] red, green, output [1:0] blue,
344 input left, right, up, down, rst, cycle, logooff,
345 input [2:0] scale);
346
347 wire border;
348 wire pixclk;
349 wire [7:0] zero = 8'b0;
350 wire clk;
351 wire [11:0] x, y;
92e851e1 352 reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
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353 reg [5:0] slowctr = 0;
354 reg [7:0] colorcycle = 0;
355 wire [11:0] realx, realy;
356
357 wire logoenb;
358 wire [2:0] mandelr, mandelg, logor, logog;
359 wire [1:0] mandelb, logob;
360
361 pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
362 .CLKIN_IN(gclk),
363 .CLKFX_OUT(pixclk),
364 .CLKIN_IBUFG_OUT(clk),
365 .LOCKED_OUT(dcmok)
366 );
367
368 SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
369 Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
370 Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
371
372 assign {red,green,blue} =
373 border ? 8'b00000000 :
374 (!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
375
376 always @(posedge vs)
377 begin
378 if (rst)
379 begin
380 xofs <= -`XRES/2;
381 yofs <= -`YRES/2;
382 colorcycle <= 0;
383 end else begin
384 if (up) yofs <= yofs + 1;
385 else if (down) yofs <= yofs - 1;
386
387 if (left) xofs <= xofs + 1;
388 else if (right) xofs <= xofs - 1;
389
390 if (slowctr == 0)
391 colorcycle <= colorcycle + 1;
392 end
393
394 if (slowctr == 12)
395 slowctr <= 0;
396 else
397 slowctr <= slowctr + 1;
398 end
399endmodule
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