]> Joshua Wise's Git repositories - mandelfpga.git/tree
Reg the init variables -- takes us to 83.842MHz! 8678 LUTs, 4694 slices post synthesis.
-rw-r--r-- 2648 FPGA.pal
-rw-r--r-- 12742 Main.v
-rw-r--r-- 859 ctoreadmemb.c
-rw-r--r-- 297 makepal.c
-rw-r--r-- 5665 mandelfpga.xcf
-rw-r--r-- 226 shnasto.cmd
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