[mandelfpga.git] / Main.v

/* 
 * MandelFPGA
 * by Joshua Wise and Chris Lu
 * 
 * An implementation of a pipelined algorithm to calculate the Mandelbrot set
 * in real time on an FPGA.
 */

`define XRES 640
`define YRES 480
`define WHIRRRRR 27

module SyncGen(
	input pixclk,
	output reg vs, hs,
	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	output wire [11:0] xoutreal, youtreal,
	output reg border);
	
	reg [11:0] x = 0, y = 0;	// Used for generating border and timing.
	assign xoutreal = x;
	assign youtreal = y;
	
	parameter XFPORCH = 16;
	parameter XSYNC = 96;
	parameter XBPORCH = 48;
	
	parameter YFPORCH = 10;
	parameter YSYNC = 2;
	parameter YBPORCH = 29;

	always @(posedge pixclk)
	begin
		if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				y <= 0;
			else
				y <= y + 1;
			x <= 0;
		end else
			x <= x + 1;
			
		if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
				yout <= 0;
			else
				yout <= yout + 1;
			xout <= 0;
		end else
			xout <= xout + 1;
		hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
		vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
		border <= (x > `XRES) || (y > `YRES);
	end
endmodule

// bits: 1.12

module NaiveMultiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output reg [12:0] out,
	output reg sign,
	output reg ovf);

	always @(posedge clk)
	begin
		{ovf,out} <=
			(((y[12] ? (x     ) : 0)   +
			  (y[11] ? (x >> 1) : 0)   +
			  (y[10] ? (x >> 2) : 0))  +
			(((y[9]  ? (x >> 3) : 0)   +
			  (y[8]  ? (x >> 4) : 0))  +
		    ((y[7]  ? (x >> 5) : 0)   +
			  (y[6]  ? (x >> 6) : 0))))+
			(((y[5]  ? (x >> 7) : 0)   +
			  (y[4]  ? (x >> 8) : 0)   +
			  (y[3]  ? (x >> 9) : 0))  +
			 ((y[2]  ? (x >> 10): 0)   +
			  (y[1]  ? (x >> 11): 0)   +
			  (y[0]  ? (x >> 12): 0)));
		sign <= xsign ^ ysign;
	end

endmodule

module Multiplier(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	output wire [12:0] out,
	output wire sign,
	output wire overflow);

	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);

endmodule

// Yuq.
module MandelUnit(
	input clk,
	input [12:0] x, y,
	input xsign, ysign,
	input [14:0] r, i,
	input rsign, isign,
	input [7:0] ibail, icuriter,
	output reg [12:0] xout, yout,
	output reg xsout, ysout,
	output reg [14:0] rout, iout,
	output reg rsout, isout,
	output reg [7:0] obail, ocuriter);

	wire [13:0] r2, i2;
	wire [14:0] ri, diff;
	wire [15:0] twocdiff;
	wire r2sign, i2sign, risign, dsign;
	wire [13:0] bigsum;
	wire bigsum_ovf;

	reg [12:0] xd, yd;
	reg ineedbaild;
	reg xsd, ysd;
	reg [7:0] ibaild, curiterd;

	assign ri[0] = 0;

	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);

	assign bigsum = r2[12:0] + i2[12:0];
	assign bigsum_ovf = bigsum[13] | r2[13] | i2[13];
	
	assign twocdiff = r2 - i2;
	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
	assign dsign = twocdiff[15];
	
	wire [15:0] twocrout = xd - diff;
	wire [15:0] twociout = yd - ri;

	always @ (posedge clk)
	begin
		xd <= x;
		yd <= y;
		xsd <= xsign;
		ysd <= ysign;
		xout <= xd;
		yout <= yd;
		xsout <= xsd;
		ysout <= ysd;
		ibaild <= ibail;
		curiterd <= icuriter;
		ineedbaild <= r[13] | r[14] | i[13] | i[14];

		// r^2 - i^2 + x
		if (xsd ^ dsign) begin
			if (twocrout[15]) begin	// diff > xd
				rout <= -twocrout;
				rsout <= dsign;
			end else begin
				rout <= twocrout;
				rsout <= xsd;
			end
		end else begin
			rout <= diff + xd;
			rsout <= xsd;	// xsd == dsign
		end
		
		// 2 * r * i + y
		if (ysd ^ risign) begin
			if (twociout[15]) begin	// ri > yd
				iout <= -twociout;
				isout <= risign;
			end else begin
				iout <= twociout;
				isout <= ysd;
			end
		end else begin
			iout <= ri + yd;
			isout <= ysd;
		end
		
		// If we haven't bailed out, and we meet any of the bailout conditions,
		// bail out now.  Otherwise, leave the bailout at whatever it was before.
		if ((ibaild == 255) && (bigsum_ovf | ineedbaild))
			obail <= curiterd;
		else
			obail <= ibaild;
		ocuriter <= curiterd + 8'b1;
	end

endmodule

module Mandelbrot(
	input mclk,
	input pixclk,
	input [11:0] x, y,
	input [13:0] xofs, yofs,
	input [7:0] colorofs,
	input [2:0] scale,
	output reg [2:0] red, green, output reg [1:0] blue);

`define MAXOUTN 11
	
	wire [12:0] rx, ry;
	wire [13:0] nx, ny;
	wire rxsign, rysign;
	
	assign nx = x + xofs;
	assign ny = y + yofs;
	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	assign rxsign = nx[13];
	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	assign rysign = ny[13];

	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
	wire [7:0] mb[`MAXOUTN:0];
	wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
	wire [7:0] curiter[`MAXOUTN:0];
	
	reg [14:0] initx, inity, initr, initi;
	reg [7:0] initci, initb;
	reg initxs, initys, initrs, initis;
	
	// Values after the number of iterations denoted by the subscript.
	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
	reg [7:0] stageci [2:1], stageb [2:1];
	reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
	
	reg [2:0] state = 3'b001;	// One-hot encoded state.
	
	// States are advanced one from what they should be, so that they'll
	// get there on the _next_ mclk.
	always @(posedge mclk)
	begin
		initx <= (state[2]) ? rx :
	            (state[0]) ? stagex[1] :
	            (state[1]) ? stagex[2] : 0;
		inity <= (state[2]) ? ry :
	               (state[0]) ? stagey[1] :
	               (state[1]) ? stagey[2] : 0;
		initr <= (state[2]) ? rx :
	               (state[0]) ? stager[1] :
	               (state[1]) ? stager[2] : 0;
		initi <= (state[2]) ? ry :
	               (state[0]) ? stagei[1] :
	               (state[1]) ? stagei[2] : 0;
		initxs <= (state[2]) ? rxsign :
	                (state[0]) ? stagexs[1] :
	                (state[1]) ? stagexs[2] : 0;
		initys <= (state[2]) ? rysign :
	                (state[0]) ? stageys[1] :
	                (state[1]) ? stageys[2] : 0;
		initrs <= (state[2]) ? rxsign :
	                (state[0]) ? stagers[1] :
	                (state[1]) ? stagers[2] : 0;
		initis <= (state[2]) ? rysign :
	                (state[0]) ? stageis[1] :
	                (state[1]) ? stageis[2] : 0;
		initb <= (state[2]) ? 8'b11111111 :
	               (state[0]) ? stageb[1] :
	               (state[1]) ? stageb[2] : 0;
		initci <= (state[2]) ? 8'b00000000 :
	                (state[0]) ? stageci[1] : 
	                (state[1]) ? stageci[2] : 0;
	end
	
	reg [7:0] out;
	
	// We detect when the state should be poked by a high negedge followed
	// by a high posedge -- if that happens, then we're guaranteed that the
	// state following the current state will be 3'b100.
	reg lastneg;
	always @(negedge mclk)
		lastneg <= pixclk;
	
	always @(posedge mclk)
	begin
		if (lastneg && pixclk)	// If a pixclk has happened, the state should be reset.
			state <= 3'b100;
		else						// Otherwise, just poke it forward.
			case(state)
			3'b001: state <= 3'b010;
			3'b010: state <= 3'b100;
			3'b100: state <= 3'b001;
			endcase
	
		// Data output handling
		if (state[0]) begin
			{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
		end
		if (state[1]) begin
			out <= ~mb[`MAXOUTN] + colorofs;
		end
		
		if (state[0]) begin		// PnR0 in, PnR2 out
			stagex[2] <= xprop[`MAXOUTN];
			stagey[2] <= yprop[`MAXOUTN];
			stager[2] <= mr[`MAXOUTN];
			stagei[2] <= mi[`MAXOUTN];
			stagexs[2] <= xsprop[`MAXOUTN];
			stageys[2] <= ysprop[`MAXOUTN];
			stagers[2] <= mrs[`MAXOUTN];
			stageis[2] <= mis[`MAXOUTN];
			stageb[2] <= mb[`MAXOUTN];
			stageci[2] <= curiter[`MAXOUTN];
		end
		
		if (state[2]) begin	// PnR2 in, PnR1 out
			stagex[1] <= xprop[`MAXOUTN];
			stagey[1] <= yprop[`MAXOUTN];
			stager[1] <= mr[`MAXOUTN];
			stagei[1] <= mi[`MAXOUTN];
			stagexs[1] <= xsprop[`MAXOUTN];
			stageys[1] <= ysprop[`MAXOUTN];
			stagers[1] <= mrs[`MAXOUTN];
			stageis[1] <= mis[`MAXOUTN];
			stageb[1] <= mb[`MAXOUTN];
			stageci[1] <= curiter[`MAXOUTN];
		end
	end

	MandelUnit mu0(
		mclk,
		initx, inity, initxs, initys,
		initr, initi, initrs, initis,
		initb, initci,
		xprop[0], yprop[0], xsprop[0], ysprop[0],
		mr[0], mi[0], mrs[0], mis[0],
		mb[0], curiter[0]);
		
`define MAKE_UNIT(name, num) \
	MandelUnit name(mclk, \
		xprop[(num)], yprop[(num)], xsprop[(num)], ysprop[(num)], mr[(num)], mi[(num)], mrs[(num)], mis[(num)], mb[(num)], curiter[(num)], \
		xprop[(num)+1], yprop[(num)+1], xsprop[(num)+1], ysprop[(num)+1], mr[(num)+1], mi[(num)+1], mrs[(num)+1], mis[(num)+1], mb[(num)+1], curiter[(num)+1])

	`MAKE_UNIT(mu1, 0);
	`MAKE_UNIT(mu2, 1);
	`MAKE_UNIT(mu3, 2);
	`MAKE_UNIT(mu4, 3);
	`MAKE_UNIT(mu5, 4);
	`MAKE_UNIT(mu6, 5);
	`MAKE_UNIT(mu7, 6);
	`MAKE_UNIT(mu8, 7);
	`MAKE_UNIT(mu9, 8);
	`MAKE_UNIT(mua, 9);
	`MAKE_UNIT(mub, 10);
endmodule

module Logo(
	input pixclk,
	input [11:0] x, y,
	output wire enb,
	output wire [2:0] red, green, output wire [1:0] blue);
	
	reg [1:0] logo[8191:0];
	initial $readmemb("logo.readmemb", logo);
	
	assign enb = (x < 96) && (y < 64);
	wire [12:0] addr = {y[5:0], x[6:0]};
	wire [1:0] data = logo[addr];
	assign {red, green, blue} = 
		 (data == 2'b00) ? 8'b00000000 :
		((data == 2'b01) ? 8'b00011100 :
		((data == 2'b10) ? 8'b11100000 :
		                    8'b11111111));
endmodule

module MandelTop(
	input gclk, output wire dcmok,
	output wire vs, hs,
	output wire [2:0] red, green, output [1:0] blue,
	input left, right, up, down, rst, cycle, logooff,
	input [2:0] scale);

	wire pixclk, mclk, clk;
	wire dcm1ok, dcm2ok;
	assign dcmok = dcm1ok && dcm2ok;
	
	IBUFG iclkbuf(.O(clk), .I(gclk));
	
	pixDCM dcm(					// CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
		.CLKIN_IN(clk), 
		.CLKFX_OUT(pixclk),
		.LOCKED_OUT(dcm1ok)
		);
	
	mandelDCM dcm2(
		.CLKIN_IN(clk),
		.CLKFX_OUT(mclk),
		.LOCKED_OUT(dcm2ok)
		);
	
	wire border;
	wire [11:0] x, y;
	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
	reg [5:0] slowctr = 0;
	reg [7:0] colorcycle = 0;
	wire [11:0] realx, realy;
	
	wire logoenb;
	wire [2:0] mandelr, mandelg, logor, logog;
	wire [1:0] mandelb, logob;
	
	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
	Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	
	assign {red,green,blue} =
		border ? 8'b00000000 :
		(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	
	always @(posedge vs)
	begin
		if (rst)
		begin
			xofs <= -`XRES/2;
			yofs <= -`YRES/2;
			colorcycle <= 0;
		end else begin
			if (up) yofs <= yofs + 1;
			else if (down) yofs <= yofs - 1;
			
			if (left) xofs <= xofs + 1;
			else if (right) xofs <= xofs - 1;
			
			if (slowctr == 0)
				colorcycle <= colorcycle + 1;
		end
		
		if (slowctr == 12)
			slowctr <= 0;
		else
			slowctr <= slowctr + 1;
	end
endmodule
Commit	Line	Data
cf1ae842	1	/*
05c0805b JW	2	* MandelFPGA
	3	* by Joshua Wise and Chris Lu
	4	*
	5	* An implementation of a pipelined algorithm to calculate the Mandelbrot set
	6	* in real time on an FPGA.
	7	*/
	8
	9	`define XRES 640
	10	`define YRES 480
281eac32	11	`define WHIRRRRR 27
05c0805b JW	12
	13	module SyncGen(
	14	input pixclk,
	15	output reg vs, hs,
	16	output reg [11:0] xout = `WHIRRRRR, yout = 0,
	17	output wire [11:0] xoutreal, youtreal,
	18	output reg border);
	19
	20	reg [11:0] x = 0, y = 0; // Used for generating border and timing.
	21	assign xoutreal = x;
	22	assign youtreal = y;
	23
	24	parameter XFPORCH = 16;
	25	parameter XSYNC = 96;
	26	parameter XBPORCH = 48;
	27
	28	parameter YFPORCH = 10;
	29	parameter YSYNC = 2;
	30	parameter YBPORCH = 29;
	31
	32	always @(posedge pixclk)
	33	begin
	34	if (x >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	35	begin
	36	if (y >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	37	y <= 0;
	38	else
	39	y <= y + 1;
	40	x <= 0;
	41	end else
	42	x <= x + 1;
	43
	44	if (xout >= (`XRES + XFPORCH + XSYNC + XBPORCH))
	45	begin
	46	if (yout >= (`YRES + YFPORCH + YSYNC + YBPORCH))
	47	yout <= 0;
	48	else
	49	yout <= yout + 1;
	50	xout <= 0;
	51	end else
	52	xout <= xout + 1;
	53	hs <= (x >= (`XRES + XFPORCH)) && (x < (`XRES + XFPORCH + XSYNC));
	54	vs <= (y >= (`YRES + YFPORCH)) && (y < (`YRES + YFPORCH + YSYNC));
	55	border <= (x > `XRES) \|\| (y > `YRES);
	56	end
	57	endmodule
	58
	59	// bits: 1.12
	60
	61	module NaiveMultiplier(
	62	input clk,
	63	input [12:0] x, y,
	64	input xsign, ysign,
	65	output reg [12:0] out,
	66	output reg sign,
fb8d158b	67	output reg ovf);
05c0805b JW	68
	69	always @(posedge clk)
	70	begin
	71	{ovf,out} <=
11cc2d9b JW	72	(((y[12] ? (x ) : 0) +
	73	(y[11] ? (x >> 1) : 0) +
	74	(y[10] ? (x >> 2) : 0)) +
	75	(((y[9] ? (x >> 3) : 0) +
	76	(y[8] ? (x >> 4) : 0)) +
	77	((y[7] ? (x >> 5) : 0) +
fb8d158b	78	(y[6] ? (x >> 6) : 0))))+
11cc2d9b JW	79	(((y[5] ? (x >> 7) : 0) +
	80	(y[4] ? (x >> 8) : 0) +
	81	(y[3] ? (x >> 9) : 0)) +
	82	((y[2] ? (x >> 10): 0) +
	83	(y[1] ? (x >> 11): 0) +
05c0805b JW	84	(y[0] ? (x >> 12): 0)));
	85	sign <= xsign ^ ysign;
	86	end
	87
	88	endmodule
	89
	90	module Multiplier(
	91	input clk,
92e851e1	92	input [12:0] x, y,
05c0805b	93	input xsign, ysign,
92e851e1	94	output wire [12:0] out,
05c0805b	95	output wire sign,
fb8d158b	96	output wire overflow);
05c0805b JW	97
	98	NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
	99
	100	endmodule
	101
fb8d158b	102	// Yuq.
05c0805b JW	103	module MandelUnit(
	104	input clk,
	105	input [12:0] x, y,
	106	input xsign, ysign,
92e851e1	107	input [14:0] r, i,
05c0805b JW	108	input rsign, isign,
	109	input [7:0] ibail, icuriter,
	110	output reg [12:0] xout, yout,
	111	output reg xsout, ysout,
92e851e1	112	output reg [14:0] rout, iout,
05c0805b JW	113	output reg rsout, isout,
	114	output reg [7:0] obail, ocuriter);
	115
6cdf39e2 JW	116	wire [13:0] r2, i2;
6cdf39e2 JW	117	wire [14:0] ri, diff;
9032b2b5	118	wire [15:0] twocdiff;
05c0805b	119	wire r2sign, i2sign, risign, dsign;
6cdf39e2 JW	120	wire [13:0] bigsum;
6cdf39e2 JW	121	wire bigsum_ovf;
05c0805b JW	122
05c0805b JW	123	reg [12:0] xd, yd;
2afeab21	124	reg ineedbaild;
05c0805b JW	125	reg xsd, ysd;
	126	reg [7:0] ibaild, curiterd;
	127
	128	assign ri[0] = 0;
	129
a3a4354b JW	130	Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
	131	Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
	132	Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
05c0805b	133
6cdf39e2 JW	134	assign bigsum = r2[12:0] + i2[12:0];
6cdf39e2 JW	135	assign bigsum_ovf = bigsum[13] \| r2[13] \| i2[13];
2afeab21	136
9032b2b5 JW	137	assign twocdiff = r2 - i2;
	138	assign diff = twocdiff[15] ? -twocdiff : twocdiff;
	139	assign dsign = twocdiff[15];
2afeab21 JW	140
	141	wire [15:0] twocrout = xd - diff;
	142	wire [15:0] twociout = yd - ri;
05c0805b JW	143
	144	always @ (posedge clk)
	145	begin
	146	xd <= x;
	147	yd <= y;
	148	xsd <= xsign;
	149	ysd <= ysign;
	150	xout <= xd;
	151	yout <= yd;
	152	xsout <= xsd;
	153	ysout <= ysd;
	154	ibaild <= ibail;
	155	curiterd <= icuriter;
2afeab21	156	ineedbaild <= r[13] \| r[14] \| i[13] \| i[14];
05c0805b	157
2afeab21	158	// r^2 - i^2 + x
05c0805b	159	if (xsd ^ dsign) begin
2afeab21 JW	160	if (twocrout[15]) begin // diff > xd
2afeab21 JW	161	rout <= -twocrout;
05c0805b JW	162	rsout <= dsign;
05c0805b JW	163	end else begin
2afeab21	164	rout <= twocrout;
05c0805b JW	165	rsout <= xsd;
	166	end
	167	end else begin
	168	rout <= diff + xd;
2afeab21	169	rsout <= xsd; // xsd == dsign
05c0805b JW	170	end
05c0805b JW	171
2afeab21	172	// 2 * r * i + y
05c0805b	173	if (ysd ^ risign) begin
2afeab21 JW	174	if (twociout[15]) begin // ri > yd
2afeab21 JW	175	iout <= -twociout;
05c0805b JW	176	isout <= risign;
05c0805b JW	177	end else begin
2afeab21	178	iout <= twociout;
05c0805b JW	179	isout <= ysd;
	180	end
	181	end else begin
	182	iout <= ri + yd;
	183	isout <= ysd;
	184	end
	185
	186	// If we haven't bailed out, and we meet any of the bailout conditions,
	187	// bail out now. Otherwise, leave the bailout at whatever it was before.
2afeab21	188	if ((ibaild == 255) && (bigsum_ovf \| ineedbaild))
05c0805b JW	189	obail <= curiterd;
	190	else
	191	obail <= ibaild;
	192	ocuriter <= curiterd + 8'b1;
	193	end
	194
	195	endmodule
	196
	197	module Mandelbrot(
	198	input mclk,
	199	input pixclk,
	200	input [11:0] x, y,
92e851e1	201	input [13:0] xofs, yofs,
05c0805b JW	202	input [7:0] colorofs,
	203	input [2:0] scale,
	204	output reg [2:0] red, green, output reg [1:0] blue);
281eac32	205
534b3903	206	`define MAXOUTN 11
05c0805b JW	207
	208	wire [12:0] rx, ry;
	209	wire [13:0] nx, ny;
	210	wire rxsign, rysign;
	211
	212	assign nx = x + xofs;
	213	assign ny = y + yofs;
	214	assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
	215	assign rxsign = nx[13];
	216	assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
	217	assign rysign = ny[13];
05c0805b	218
281eac32 JW	219	wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
	220	wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
	221	wire [7:0] mb[`MAXOUTN:0];
	222	wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
	223	wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
	224	wire [7:0] curiter[`MAXOUTN:0];
05c0805b	225
79af494a JW	226	reg [14:0] initx, inity, initr, initi;
	227	reg [7:0] initci, initb;
	228	reg initxs, initys, initrs, initis;
05c0805b	229
534b3903 JW	230	// Values after the number of iterations denoted by the subscript.
	231	reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
	232	reg [7:0] stageci [2:1], stageb [2:1];
	233	reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
05c0805b	234
534b3903	235	reg [2:0] state = 3'b001; // One-hot encoded state.
05c0805b	236
79af494a JW	237	// States are advanced one from what they should be, so that they'll
	238	// get there on the _next_ mclk.
	239	always @(posedge mclk)
	240	begin
	241	initx <= (state[2]) ? rx :
	242	(state[0]) ? stagex[1] :
	243	(state[1]) ? stagex[2] : 0;
	244	inity <= (state[2]) ? ry :
	245	(state[0]) ? stagey[1] :
	246	(state[1]) ? stagey[2] : 0;
	247	initr <= (state[2]) ? rx :
	248	(state[0]) ? stager[1] :
	249	(state[1]) ? stager[2] : 0;
	250	initi <= (state[2]) ? ry :
	251	(state[0]) ? stagei[1] :
	252	(state[1]) ? stagei[2] : 0;
	253	initxs <= (state[2]) ? rxsign :
	254	(state[0]) ? stagexs[1] :
	255	(state[1]) ? stagexs[2] : 0;
	256	initys <= (state[2]) ? rysign :
	257	(state[0]) ? stageys[1] :
	258	(state[1]) ? stageys[2] : 0;
	259	initrs <= (state[2]) ? rxsign :
	260	(state[0]) ? stagers[1] :
	261	(state[1]) ? stagers[2] : 0;
	262	initis <= (state[2]) ? rysign :
	263	(state[0]) ? stageis[1] :
	264	(state[1]) ? stageis[2] : 0;
	265	initb <= (state[2]) ? 8'b11111111 :
	266	(state[0]) ? stageb[1] :
	267	(state[1]) ? stageb[2] : 0;
	268	initci <= (state[2]) ? 8'b00000000 :
	269	(state[0]) ? stageci[1] :
	270	(state[1]) ? stageci[2] : 0;
	271	end
05c0805b JW	272
05c0805b JW	273	reg [7:0] out;
251788d8 JW	274
251788d8 JW	275	// We detect when the state should be poked by a high negedge followed
fb8d158b JW	276	// by a high posedge -- if that happens, then we're guaranteed that the
fb8d158b JW	277	// state following the current state will be 3'b100.
251788d8	278	reg lastneg;
265061f2	279	always @(negedge mclk)
251788d8	280	lastneg <= pixclk;
05c0805b JW	281
	282	always @(posedge mclk)
	283	begin
251788d8 JW	284	if (lastneg && pixclk) // If a pixclk has happened, the state should be reset.
	285	state <= 3'b100;
	286	else // Otherwise, just poke it forward.
a3a4354b JW	287	case(state)
	288	3'b001: state <= 3'b010;
	289	3'b010: state <= 3'b100;
	290	3'b100: state <= 3'b001;
	291	endcase
251788d8	292
534b3903 JW	293	// Data output handling
534b3903 JW	294	if (state[0]) begin
05c0805b	295	{red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
05c0805b	296	end
3068fa61	297	if (state[1]) begin
534b3903 JW	298	out <= ~mb[`MAXOUTN] + colorofs;
	299	end
	300
3068fa61	301	if (state[0]) begin // PnR0 in, PnR2 out
534b3903 JW	302	stagex[2] <= xprop[`MAXOUTN];
	303	stagey[2] <= yprop[`MAXOUTN];
	304	stager[2] <= mr[`MAXOUTN];
	305	stagei[2] <= mi[`MAXOUTN];
	306	stagexs[2] <= xsprop[`MAXOUTN];
	307	stageys[2] <= ysprop[`MAXOUTN];
	308	stagers[2] <= mrs[`MAXOUTN];
	309	stageis[2] <= mis[`MAXOUTN];
	310	stageb[2] <= mb[`MAXOUTN];
	311	stageci[2] <= curiter[`MAXOUTN];
	312	end
	313
3068fa61	314	if (state[2]) begin // PnR2 in, PnR1 out
534b3903 JW	315	stagex[1] <= xprop[`MAXOUTN];
	316	stagey[1] <= yprop[`MAXOUTN];
	317	stager[1] <= mr[`MAXOUTN];
	318	stagei[1] <= mi[`MAXOUTN];
	319	stagexs[1] <= xsprop[`MAXOUTN];
	320	stageys[1] <= ysprop[`MAXOUTN];
	321	stagers[1] <= mrs[`MAXOUTN];
	322	stageis[1] <= mis[`MAXOUTN];
	323	stageb[1] <= mb[`MAXOUTN];
	324	stageci[1] <= curiter[`MAXOUTN];
	325	end
05c0805b JW	326	end
	327
	328	MandelUnit mu0(
	329	mclk,
	330	initx, inity, initxs, initys,
	331	initr, initi, initrs, initis,
	332	initb, initci,
	333	xprop[0], yprop[0], xsprop[0], ysprop[0],
	334	mr[0], mi[0], mrs[0], mis[0],
	335	mb[0], curiter[0]);
e03ccef9 JW	336
	337	`define MAKE_UNIT(name, num) \
	338	MandelUnit name(mclk, \
	339	xprop[(num)], yprop[(num)], xsprop[(num)], ysprop[(num)], mr[(num)], mi[(num)], mrs[(num)], mis[(num)], mb[(num)], curiter[(num)], \
	340	xprop[(num)+1], yprop[(num)+1], xsprop[(num)+1], ysprop[(num)+1], mr[(num)+1], mi[(num)+1], mrs[(num)+1], mis[(num)+1], mb[(num)+1], curiter[(num)+1])
05c0805b	341
e03ccef9 JW	342	`MAKE_UNIT(mu1, 0);
	343	`MAKE_UNIT(mu2, 1);
	344	`MAKE_UNIT(mu3, 2);
	345	`MAKE_UNIT(mu4, 3);
	346	`MAKE_UNIT(mu5, 4);
	347	`MAKE_UNIT(mu6, 5);
	348	`MAKE_UNIT(mu7, 6);
	349	`MAKE_UNIT(mu8, 7);
	350	`MAKE_UNIT(mu9, 8);
	351	`MAKE_UNIT(mua, 9);
	352	`MAKE_UNIT(mub, 10);
05c0805b JW	353	endmodule
	354
	355	module Logo(
	356	input pixclk,
	357	input [11:0] x, y,
	358	output wire enb,
	359	output wire [2:0] red, green, output wire [1:0] blue);
	360
	361	reg [1:0] logo[8191:0];
	362	initial $readmemb("logo.readmemb", logo);
	363
	364	assign enb = (x < 96) && (y < 64);
	365	wire [12:0] addr = {y[5:0], x[6:0]};
	366	wire [1:0] data = logo[addr];
	367	assign {red, green, blue} =
	368	(data == 2'b00) ? 8'b00000000 :
	369	((data == 2'b01) ? 8'b00011100 :
	370	((data == 2'b10) ? 8'b11100000 :
	371	8'b11111111));
	372	endmodule
	373
	374	module MandelTop(
	375	input gclk, output wire dcmok,
	376	output wire vs, hs,
	377	output wire [2:0] red, green, output [1:0] blue,
	378	input left, right, up, down, rst, cycle, logooff,
	379	input [2:0] scale);
	380
11cc2d9b	381	wire pixclk, mclk, clk;
534b3903	382	wire dcm1ok, dcm2ok;
c3ed4329	383	assign dcmok = dcm1ok && dcm2ok;
265061f2	384
e03ccef9	385	IBUFG iclkbuf(.O(clk), .I(gclk));
534b3903	386
c3ed4329 JW	387	pixDCM dcm( // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
	388	.CLKIN_IN(clk),
	389	.CLKFX_OUT(pixclk),
	390	.LOCKED_OUT(dcm1ok)
	391	);
534b3903	392
c3ed4329 JW	393	mandelDCM dcm2(
	394	.CLKIN_IN(clk),
	395	.CLKFX_OUT(mclk),
	396	.LOCKED_OUT(dcm2ok)
	397	);
534b3903	398
05c0805b	399	wire border;
05c0805b	400	wire [11:0] x, y;
92e851e1	401	reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
05c0805b JW	402	reg [5:0] slowctr = 0;
	403	reg [7:0] colorcycle = 0;
	404	wire [11:0] realx, realy;
	405
	406	wire logoenb;
	407	wire [2:0] mandelr, mandelg, logor, logog;
	408	wire [1:0] mandelb, logob;
	409
05c0805b	410	SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
534b3903	411	Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
05c0805b JW	412	Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
	413
	414	assign {red,green,blue} =
	415	border ? 8'b00000000 :
	416	(!logooff && logoenb) ? {logor, logog, logob} : {mandelr, mandelg, mandelb};
	417
	418	always @(posedge vs)
	419	begin
	420	if (rst)
	421	begin
	422	xofs <= -`XRES/2;
	423	yofs <= -`YRES/2;
	424	colorcycle <= 0;
	425	end else begin
	426	if (up) yofs <= yofs + 1;
	427	else if (down) yofs <= yofs - 1;
	428
	429	if (left) xofs <= xofs + 1;
	430	else if (right) xofs <= xofs - 1;
	431
	432	if (slowctr == 0)
	433	colorcycle <= colorcycle + 1;
	434	end
	435
	436	if (slowctr == 12)
	437	slowctr <= 0;
	438	else
	439	slowctr <= slowctr + 1;
	440	end
	441	endmodule