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[fpgaboy.git] / System.v
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a85b19a7
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
fe3dc890 9 reg [7:0] rom [1023:0];
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10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
fe3dc890 13 wire [7:0] odata = rom[address[10:0]];
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14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
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18module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] ram [127:0];
25
26 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27 reg [7:0] odata;
28 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29
30 always @(negedge clk)
31 begin
32 if (decode) // This has to go this way. The only way XST knows how to do
33 begin // block ram is chip select, write enable, and always
34 if (wr) // reading. "else if rd" does not cut it ...
35 ram[address[6:0]] <= data;
36 odata <= ram[address[6:0]];
37 end
38 end
c279b666 39endmodule
6bd4619b 40
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41module InternalRAM(
42 input [15:0] address,
43 inout [7:0] data,
44 input clk,
45 input wr, rd);
46
fe3dc890 47 // synthesis attribute ram_style of ram is block
616eebe0 48 reg [7:0] ram [8191:0];
a85b19a7 49
c87db60a 50 wire decode = address[15:13] == 3'b110;
a85b19a7 51 reg [7:0] odata;
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52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
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56 if (decode) // This has to go this way. The only way XST knows how to do
57 begin // block ram is chip select, write enable, and always
58 if (wr) // reading. "else if rd" does not cut it ...
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59 ram[address[12:0]] <= data;
60 odata <= ram[address[12:0]];
c87db60a 61 end
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62 end
63endmodule
64
65module Switches(
66 input [15:0] address,
67 inout [7:0] data,
68 input clk,
69 input wr, rd,
70 input [7:0] switches,
9c834ff2 71 output reg [7:0] ledout = 0);
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72
73 wire decode = address == 16'hFF51;
74 reg [7:0] odata;
75 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
76
77 always @(negedge clk)
78 begin
79 if (decode && rd)
80 odata <= switches;
81 else if (decode && wr)
82 ledout <= data;
83 end
84endmodule
85
86module CoreTop(
87 input xtal,
88 input [7:0] switches,
ff7fd7f2 89 input [3:0] buttons,
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90 output wire [7:0] leds,
91 output serio,
92 output wire [3:0] digits,
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93 output wire [7:0] seven,
94 output wire hs, vs,
95 output wire [2:0] r, g,
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96 output wire [1:0] b,
97 output wire soundl, soundr);
a85b19a7 98
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99 wire xtalb, clk, vgaclk;
100 IBUFG iclkbuf(.O(xtalb), .I(xtal));
101 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
102 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
6c46357c 103
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104 wire [15:0] addr;
105 wire [7:0] data;
106 wire wr, rd;
f8db6448 107
00573fd5 108 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 109 wire [7:0] jaddr;
6c46357c 110 wire [1:0] state;
179b4347 111
a85b19a7 112 GBZ80Core core(
179b4347 113 .clk(clk),
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114 .busaddress(addr),
115 .busdata(data),
116 .buswr(wr),
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117 .busrd(rd),
118 .irq(irq),
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119 .jaddr(jaddr),
120 .state(state));
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121
122 ROM rom(
123 .address(addr),
124 .data(data),
125 .clk(clk),
126 .wr(wr),
127 .rd(rd));
128
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129 wire lcdhs, lcdvs, lcdclk;
130 wire [2:0] lcdr, lcdg;
131 wire [1:0] lcdb;
132
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133 LCDC lcdc(
134 .addr(addr),
135 .data(data),
136 .clk(clk),
137 .wr(wr),
138 .rd(rd),
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139 .lcdcirq(lcdcirq),
140 .vblankirq(vblankirq),
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141 .lcdclk(lcdclk),
142 .lcdhs(lcdhs),
143 .lcdvs(lcdvs),
144 .lcdr(lcdr),
145 .lcdg(lcdg),
146 .lcdb(lcdb));
147
148 Framebuffer fb(
149 .lcdclk(lcdclk),
150 .lcdhs(lcdhs),
151 .lcdvs(lcdvs),
152 .lcdr(lcdr),
153 .lcdg(lcdg),
154 .lcdb(lcdb),
155 .vgaclk(vgaclk),
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156 .vgahs(hs),
157 .vgavs(vs),
158 .vgar(r),
159 .vgag(g),
160 .vgab(b));
537e1f83 161
a85b19a7 162 AddrMon amon(
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163 .addr(addr),
164 .clk(clk),
165 .digit(digits),
166 .out(seven),
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167 .freeze(buttons[0]),
168 .periods(
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169 (state == 2'b00) ? 4'b0010 :
170 (state == 2'b01) ? 4'b0001 :
171 (state == 2'b10) ? 4'b1000 :
172 4'b0100) );
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173
174 Switches sw(
175 .address(addr),
176 .data(data),
177 .clk(clk),
178 .wr(wr),
179 .rd(rd),
180 .ledout(leds),
fc443a4f 181 .switches(switches)
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182 );
183
06ad3a30 184 UART nouart ( /* no u */
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185 .clk(clk),
186 .wr(wr),
187 .rd(rd),
188 .addr(addr),
189 .data(data),
190 .serial(serio)
191 );
9aa931d1 192
eb0f2fe1 193 InternalRAM ram(
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194 .address(addr),
195 .data(data),
196 .clk(clk),
197 .wr(wr),
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198 .rd(rd)
199 );
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200
201 MiniRAM mram(
202 .address(addr),
203 .data(data),
204 .clk(clk),
205 .wr(wr),
206 .rd(rd)
207 );
06ad3a30 208
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209 Timer tmr(
210 .clk(clk),
211 .wr(wr),
212 .rd(rd),
213 .addr(addr),
214 .data(data),
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215 .irq(tmrirq)
216 );
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217
218 Interrupt intr(
219 .clk(clk),
220 .rd(rd),
221 .wr(wr),
222 .addr(addr),
223 .data(data),
00573fd5 224 .vblank(vblankirq),
537e1f83 225 .lcdc(lcdcirq),
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226 .tovf(tmrirq),
227 .serial(0),
228 .buttons(0),
229 .master(irq),
230 .jaddr(jaddr));
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231
232 Soundcore sound(
233 .core_clk(clk),
234 .rd(rd),
235 .wr(wr),
236 .addr(addr),
237 .data(data),
238 .snd_data_l(soundl),
239 .snd_data_r(soundr));
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240endmodule
241
242module TestBench();
62940da0 243 reg clk = 1;
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244 wire [15:0] addr;
245 wire [7:0] data;
246 wire wr, rd;
247
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248 wire irq, tmrirq;
249 wire [7:0] jaddr;
250
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251 wire [7:0] leds;
252 wire [7:0] switches;
a85b19a7 253
179b4347 254 always #62 clk <= ~clk;
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255 GBZ80Core core(
256 .clk(clk),
257 .busaddress(addr),
258 .busdata(data),
259 .buswr(wr),
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260 .busrd(rd),
261 .irq(irq),
262 .jaddr(jaddr));
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263
264 ROM rom(
265 .clk(clk),
266 .address(addr),
267 .data(data),
268 .wr(wr),
269 .rd(rd));
270
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271 InternalRAM ram(
272 .address(addr),
273 .data(data),
274 .clk(clk),
275 .wr(wr),
276 .rd(rd));
a85b19a7 277
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278 wire serio;
279 UART uart(
280 .addr(addr),
281 .data(data),
282 .clk(clk),
283 .wr(wr),
284 .rd(rd),
285 .serial(serio));
a85b19a7 286
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287 Timer tmr(
288 .clk(clk),
289 .wr(wr),
290 .rd(rd),
291 .addr(addr),
292 .data(data),
293 .irq(tmrirq));
294
295 Interrupt intr(
296 .clk(clk),
297 .rd(rd),
298 .wr(wr),
299 .addr(addr),
300 .data(data),
301 .vblank(0),
302 .lcdc(0),
303 .tovf(tmrirq),
304 .serial(0),
305 .buttons(0),
306 .master(irq),
307 .jaddr(jaddr));
308
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309 Switches sw(
310 .clk(clk),
311 .address(addr),
312 .data(data),
313 .wr(wr),
314 .rd(rd),
315 .switches(switches),
316 .ledout(leds));
a85b19a7 317endmodule
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