]> Joshua Wise's Git repositories - fpgaboy.git/history - System.v
Add a dirty hack to make the sim pipe directly to the readout script.
[fpgaboy.git] / System.v
2008-05-04 Joshua WiseDual bus processor
2008-05-03 Joshua WiseAdd some verilator and isim compatibility
2008-04-28 Joshua WiseCompiles
2008-04-19 Joshua Wisealu_ext
2008-04-19 Joshua WiseAdd bootrom
2008-04-14 Joshua WiseCut one at a framebuffer
2008-04-14 Joshua WiseSome LCDC IRQ stuffs. Working on fixing ldm_a
2008-04-13 Joshua WiseAdd mock up LCDC
2008-04-07 Joshua WiseWire switches back up and remove cclk.
2008-04-07 Joshua WiseIt works, but why?
2008-04-06 Joshua WisePUSH bugfix
2008-04-06 Joshua WiseClean up some warnings.
2008-04-06 Joshua WiseSome reworks to prepare for transition to makefile...
2008-04-05 Joshua WiseCut 1 at interrupt support for CPU
2008-04-04 Joshua WiseTimer works.
2008-04-04 Joshua WiseFirst cut at timer
2008-04-03 Joshua WiseAdd buildrom.sh. Add some comments of note in System.v.
2008-04-02 Joshua WiseAdd a ROM, and go up to 8k of RAM
2008-04-02 Joshua WiseWorking RAM :D
2008-04-02 Joshua WiseAdd files, and add a freezeswitch to debug this issue...
2008-04-01 Joshua WiseTest RAM
2008-04-01 Joshua WisePoke the UART with a stick. ABABABABABABAB
2008-04-01 Joshua WiseJP
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